43.6.7 Interrupts

The ADC module provides two interrupts to the NVIC: one Global Interrupt (REQ0) and one Module-specific interrupts (REQ1). Global interrupts are serviced by the CTLINTENCLR, CTLINTENSET, and CTLINTFLAG registers, while each ADC Module’s interrupts are serviced by INTENCLR, INTENSET, and INTFLAG registers.

When the ADC’s chosen voltage reference status changes (not ready to ready or the reverse) the CTLINTFLAG.VREFUPD bit will be set. For this bit to fire the global interrupt CTLINTENSET.VREFUPD should be set to one. The ADC’s global interrupt ISR should always check this flag and disable ADC operation when CTLINTFLAG.VREFUPD = 1 and CTLINTFLAG.VREFRDY = 0, indicating that the voltage reference is no longer “ready” and therefore no longer useable.

When the startup delay for each ADC Module has elapsed a CRRDYn bit in the CTLINTFLAG register will go high. This can trigger a global interrupt as well if the corresponding bit in CTLINTENSET has been set. Note that the CRRDYn bit in INTFLAG will stay high and therefore continue to fire the global interrupt unless the global interrupt service routine disables the Core Ready Interrupts from firing by setting the CTLINTENCLR.CRRDYn bits to one before exiting.

Other bits in the CTLINTFLAG register are related to the operation of the APB Data FIFO. The CTLINTFLAG.PFFHFUL bit goes high when the FIFO is half full. The CTLINTFLAG.PFFRDY goes high when the FIFO is “ready”, i.e. when it contains data to be ready. FIFO overflow and underflow will set the CTLINTFLAG.PFFOVF or CTLINTFLAG.PFFUNF bits, respectively.