3.1.2 SPI - Serial Peripheral Interface

A clarification has been made to the Operation - Client Mode - Buffer Mode section.

28.3.2.2.2 Buffer Mode

To avoid data collisions, the SPI peripheral can be configured in Buffered mode by writing a ‘1’ to the Buffer Mode Enable (BUFEN) bit in the Control B (SPIn.CTRLB) register.

In this mode, the SPI has additional interrupt flags and extra buffers. The extra buffers are shown in Figure 28-1. There are two different modes for the Buffer mode, selected with the Buffer mode Wait for Receive (BUFWR) bit. The two different modes are described below with timing diagrams.

Note: When operating as a client in Buffered mode and the SPI clock is close to maximum frequency, the client may not be able to set up data in time for the first sample edge during back-to-back transfers. Refer to the Electrical Characteristics - SPI section for details.