1.1.3 TE0 Error Detection Does Not Take R/W Bit Into Consideration

An I3C Target should detect TE0 error by monitoring the bus for any of the following invalid combinations of Broadcast Address/W:

  • 7’h3E/W
  • 7’h5E/W
  • 7’h6E/W
  • 7’h76/W
  • 7’h7A/W
  • 7’h7C/W
  • 7’h7F/W
  • 7’h7E/R

With the exception of 7'h7E/R, the module flags a TE0 error immediately after the 7-bit address match happens, regardless of the status of the R/W bit.

Work around

None. However, the I3C Controller on the bus can send an HDR Exit Pattern for error recovery if the target device appears unresponsive on the bus.

Affected Silicon Revisions

A0
X