1.1.3.1 MSS_DDR 16-bit Width with ECC Enabled

Updated MSS Configurator component XML to enable correct ECC byte-lane and ensure successful DDR memory training.

Note: MPFS HAL versions later than v2.3.105 is required from the PolarFire SoC GitHub to use this change.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.