7 AC/DC Characteristics and Timing Requirements

Table 7-1 lists the AC/DC characteristics and timing requirements.

Table 7-1. AC/DC Characteristics and Timing Requirements
Standard Operating Conditions Operating Temperature: -40ºC to +125ºC. Programming at +25ºC is recommended.
Param. No.	Symbol	Characteristic	Min.	Max.	Units	Conditions
D111	V_DD	Supply Voltage During Programming	3.0	3.60	V	Normal programming⁽¹⁾
D113	I_DDP	Supply Current During Programming	—	10	mA
D114	I_PEAK	Instantaneous Peak Current During Start-up	—	200	mA
D031	V_IL	Input Low Voltage	Vss	0.2 Vdd	V
D041	V_IH	Input High Voltage	0.7 Vdd	Vdd	V
D080	V_OL	Output Low Voltage	—	0.4	V
D090	V_OH	Output High Voltage	2.4	—	V
D012	C_IO	Capacitive Loading on I/O Pin (PGEDx)	—	50	pF
P1	T_PGC	Serial Clock (PGECx) Period (ICSP™)	200	—	ns
P1	T_PGC	Serial Clock (PGECx) Period (Enhanced ICSP)	500	—	ns
P1A	T_PGCL	Serial Clock (PGECx) Low Time (ICSP)	80	—	ns
P1A	T_PGCL	Serial Clock (PGECx) Low Time (Enhanced ICSP)	200	—	ns
P1B	T_PGCH	Serial Clock (PGECx) High Time (ICSP)	80	—	ns
P1B	T_PGCH	Serial Clock (PGECx) High Time (Enhanced ICSP)	200	—	ns
P2	T_SET1	Input Data Setup Time to Serial Clock ↓	15	—	ns
P3	T_HLD1	Input Data Hold Time from PGECx ↓	15	—	ns
P4	T_DLY1	Delay Between 4-Bit Command and Command Operand	40	—	ns
P4A	T_DLY1A	Delay Between Command Operand and Next 4-Bit Command	40	—	ns
P5	T_DLY2	Delay Between Last PGECx ↓ of Command to First PGECx ↑ of Read of Data Word	20	—	ns
P6	T_SET2	V_DD Setup Time to MCLR	100	—	ns
P7	T_HLD2	Input Data Hold Time from MCLR ↑	50	—	ms
P8	T_DLY3	Delay Between Last PGECx ↓ of Command Byte to PGEDx ↑ by PE	12	—	µs
P9A	T_DLY4	Programming Executive Command Processing Time	10	—	µs
P9B	T_DLY5	Delay Between PGEDx ↓ by Programming Executive to PGEDx Released by Programming Executive	15	23	µs
P10	T_DLY6	PGECx Low Time After Programming	400	—	ns
P11	T_DLY7	Bulk Erase Time	—	20.0	ms	See Note 2.
P12	T_DLY8	Page Erase Time	—	20.0	ms	See Note 2.
P13	T_DLY9	Double-Word Write Time	—	52.3	µs	See Note 2.
		Row Write Time		2.2	ms	See Note 2.
P14	T_R	MCLR Rise Time to Enter ICSP mode	—	1.0	µs
P15	T_VALID	Data Out Valid from PGECx ↑	10	—	ns
P16	T_DLY10	Delay Between Last PGECx ↓ and MCLR ↑	0	—	s
P17	T_HLD3	MCLR ↓ to V_DD ↓	100	—	ns
P18	T_KEY1	Delay from First MCLR ↓ to First PGECx ↑ for Key Sequence on PGEDx	1	—	ms
P19	T_KEY2	Delay from Last PGECx ↓ for Key Sequence on PGEDx to Second MCLR ↑	25	—	ns
P21	T_MCLRH	MCLR High Time	—	500	µs
Note: V_DD must also be supplied to the AV_DD pins during programming. AV_DD and AV_SS should always be within ±0.3V of V_DD and V_SS, respectively. Time depends on the FRC accuracy and the value of the FRC Oscillator Tuning register. Refer to the “Electrical Characteristics” chapter in the specific device data sheet.