1.1.5 Clear Command May Not Work Properly in Asynchronous Mode
When operating in asynchronous mode (CSYNC = 0), setting the Clear
Command bit (CLR= 1) may not clear the Timer Counter register
value.
Work around
Use the Universal Timer module in synchronous mode (CSYNC = 1) when
Clear Command bit (CLR) is being used.
Affected Silicon Revisions
| B3 | B4 | B5 | C0 |
| X | X | X | X |