Silicon Errata Issues

The ADC level trigger does not perform burst conversions in Debug mode.

The scan list conversions defined in the ADCCSS1 register will restart without finishing the current scan list and does not generate an EOSRDY bit (ADCCON2[29]) end of scan interrupt status if a new trigger event from the STRGSRC[4:0]bits (ADCCON1[20:16]) trigger source occurs before the scan list completion on the shared ADC core.

AC_CMPx output is not gated either by COMPCTRLx.ENABLE or PMD1.ACMD.

AC_CMP0 is supposed to use a fixed VDD/2 reference when the VDD scaler option is used. But the observed reference voltage is not equal to VDD/2.

The wrong VDD scaler reference voltage is observed when AC_CMP0 and AC_CMP1 are enabled concurrently with VDD scaler as the reference for both the comparators. Both the comparators will see the same VDD scaler reference.

The Power-on Reset value of the PB3 clock is not correct.

The SEQCTRLx and LUCTRLx registers are enable-protected by the CTRL.ENABLE bit; however, they must be enable-protected by the LUTCTRLx.ENABLE bits.

LUT output is corrupted after enabling CCL when sequential logic is used.

There is degraded VIL/VIH performance when the GPIO pull-up/pull-down resistors are enabled on PB0, PB1, PB2, PB3,PB4, PB5, PB6, PB8 or PB9. These pins may not be able to recognize a logic low level if the pull-up on that pad is enabled.

Device debugging or programming can only be supported using ICD4 at room temperature. When programming or debugging, the device’s supply voltage can only range between 1.9 (min) and 3.0 (max) V, including the min and max voltages.

The DSU CRC32 will not complete when targeting NVM memory space while the NVM cache is disabled.

In Debug mode, DMAC does not restart after a debug halt when DBGCTRL.DBGRUN = 0.

When at least one channel using linked descriptors is already active, a channel Fetch Error (FERR) may occur on enabling a channel with no linked descriptor or when one of the already active channels using linked descriptors may fetch the enabled second descriptor (index 1) of the channel. These errors can occur when a channel is enabled during the link request of another channel and if the channel number of the enabled channel is lower than the already active channel.

When enabling EIC, the SYNCBUSY.ENABLE bit resets before EIC is fully enabled. Edge detection can be done only after three cycles of the selected GCLK (GCLK_EIC or CLK_ULP32K).

When the asynchronous edge detection is enabled and the system is in Standby mode, only the first edge will be detected. The following edges are ignored until the system wakes up.

BUSYCH flag never resets upon software events in synchronous/resynchronized path modes with event detection on falling edges.

If a software event occurs when the EVSYS is set in synchronous/resynchronized path modes (CHANNELn.PATH=0x0/0x1) with event detection set on falling edges (CHANNELn.EDGSEL=0x2), the CHSTATUS.BUSYCHn flag will be set but will never come back to 0. It is, then, impossible to know if the event user for this channel is ready to accept new events or not.

Overrun interrupt flag may be incorrectly set upon software events in synchronous/resynchronized path modes with event detection on both rising and falling edges.

If a software event occurs when the EVSYS is set in synchronous/resynchronized path modes (CHANNELn.PATH=0x0/0x1) with event detection set on both rising and falling edges (CHANNELn.EDGSEL=0x3), spurious overrun interrupts may occur (INTFLAG.OVRn).

During a measurement slot, the measurement clock stalls (or is very slow), the STATUS.BUSY will never de-assert and the DONE interrupt will not be raised.

In Deep Sleep and Extreme Deep Sleep Mode, do not set GPIO to output state of pin high.

Configuring the GPIO state to pin high during Deep Sleep and Extreme Deep Sleep Mode will cause leakage current and potential reliability issues on the silicon.

This issue is only applicable when the system is in Deep Sleep or Extreme Deep Sleep Mode and when GPIO is configured as output state pin high.

FREQM reads on the Control B register (FREQM.CTRLB) generate a PAC protection error.

Writing the Software Reset bit in the Control A register (CTRLASWRST) will trigger a PAC protection error.

CHECON.ADRWS is not hard wired to ‘0’ and is configurable to ‘1’ or ‘0’, with the reset/default value being ‘1’. The CPU hangs when the CHECON.ADRWS configuration switches from ‘1’ to ‘0’ and a Flash read access occurs. While CHECON.ADRWS is switching to ‘0’ (default is ‘1’), the ADRWS will be latched at the next clock, and, if a Flash read access happens at the same clock, the system hangs waiting for an internal ack due to the PFM cache miss.

If PB2_CLK is not equal to System Clock (sys_clk), ERRADDR register read will not return the failing address (caused by Single Bit Error/Dual Bit Error); instead it may return ‘0’.

False tamper detections may occur when configuring the RTC INn and OUTn pins.

General Purpose Registers n (GPn) are Reset on tamper detection even if GPTRST = 0.

When DMA is enabled (CTRLB.DMAEN = 1), the INTFLAG.TAMPER bit is not reset by reading the TIMESTAMP register.

Entering the Deep Sleep mode without waiting for SYNCBUSY.ENABLE and SYNCBUSY.COUNTSYNC synchronization completion may freeze these bits’ statuses.

When COUNTSYNC is enabled, the first COUNT value is not correctly synchronized and, thus, it is an incorrect value.

Majority debouncing, as part of RTC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ.

Upon enabling the RTC tamper detection feature, a false tamper detection can be reported by the RTC.

If an external reset occurs during a tamper detection, the timestamp register will not be updated when the next tamper detection is triggered.

When CTRLA.PRESCALER is set to OFF and either CTRLB.RTCOUT is set or one of the TAMCTRL.DEBNCn bits is set, the RTC prescaler behaves like CTRLA.PRESCALER = DIV1. The periodic events and periodic interrupts will be generated.

When the USART is used in the 32-bit mode with hardware handshaking (CTS/RTS), the TXC flag may be set before transmission has completed. TXC may incorrectly be set regardless of whether Data Length Enable (LENGTH.LENEN) is set to ‘0’ or ‘1’.

When the SERCOM USART configured as CTRLA.RUNSTDBY = 0 and the Receiver is disabled (CTRLB.RXEN = 0), the clock request to the SERCOM generic clock generator feeding the SERCOM will stay asserted during the Standby Sleep mode, leading to unexpected overconsumption.

In USART Auto-Baud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.

In USART operating mode with Collision Detection enabled (CTRLB.COLDEN = 1), the SERCOM will not abort the current transfer as expected if a collision is detected and if the SERCOM APB Clock is lower than the SERCOM Generic Clock.

In USART operating mode, if DBGCTRL.DBGSTOP = 1, data transmission is not halted after entering Debug mode.

The SERCOM USART does not wake from the Standby Sleep mode for ERROR interrupts FERR and PERR.

When the 32-bit Extension mode is enabled and data to be sent are not in multiples of 4 bytes, which means the length counter must be enabled, additional bytes will be sent over the line.

The TXINV and RXINV bits in CTRLA are interchanged. TXINV controls the RX signal inversion and RXINV controls the TX signal inversion.

The STATUS.CLKHOLD bit in host and client modes can be written even though it is specified as a read-only status bit.

The I²C client AACKEN feature is not usable when doing a repeated start.

When an unexpected STOP occurs on the I²C bus, the STATUS.BUSERR and INTFLAG.ERROR bits are set but may not wake the system from the Standby Sleep mode. An unexpected START will not produce this issue.

For the Host Write operations (excluding the High-Speed mode), in 10-bit addressing mode, writing CTRLB.CMD = 0x1 does not issue a Repeated Start command correctly.

In I²C mode, LENERR, SEXTOUT, LOWTOUT, COLL and BUSERR bits are not cleared when INTFLAG.AMATCH is cleared.

In I²C Client Transmitter mode, at the reception of a NACK, if there is still data to be sent in the DMA buffer, the DMA will push a data to the DATA register. Because a NACK was received, the transfer on the I ²C bus will not occur, causing the loss of this data.

When SERCOM is configured as an I²C client in 32-bit Data mode (DATA32B = 1) and the I²C host reads from the I²C client (client transmitter) and outputs its NACK (indicating no more data is needed), the I²C client still receives a DRDY interrupt.

If the CPU does not write new data to the I²C client DATA register, I²C client will pull the SDA line, which will result in stalling the bus permanently.

The 10-bit addressing in I²C Client mode is not functional.

When the quick command is enabled (CTRLB.QCEN = 1), software can issue a repeated start by writing either CTRLB.CMD or ADDR.ADDR bit fields. If, in these conditions, SCL Stretch mode is CTRLA.SCLSM = 1, a bus error will be generated.

In SPI Client mode and with Client Data Preload Enabled (CTRLB.PLOADEN = 1), the first data sent from the client will be a dummy byte if the host cannot keep the client select (SS) line low until the end of transmission.

Preloading new SPI data (CTRLB.PLOADEN = 1) before going into Standby Sleep mode may lead to extra power consumption.

When hardware client select control is enabled (CTRLB.MSSEN = 1), the client select (SS) pin goes high after each byte transfer even if new data is ready to be sent.

When accessing peripherals on the PB-PIC bus, an access beyond the implemented memory region 0x4401_FFFF causes the CPU to hang, waiting for a bus error signal.

CFGCON0.SWOEN is non-functional, which makes PB7 function as SWO during debugging only. PB7 works normally when not doing debug.

The Power-on Reset values of the CFGPGQOS register sets all bus host QoS values to zero (Background) instead of the required Power-on Reset values.

The Timer/Counter counting-down mode (CTRLBCLR.DIR = CTRLBSET.DIR = 1) is not supported in RAMP2 operations (RAMP2, RAMP2A, RAMP2C, RAMP2CS).

In 2RAMP mode with Hi-resolution, multiple restarts can be observed when a fault occurs.

When the TCC is used in the Down-Counting mode, transfer of the PERBUF register value to the PER register is delayed by one counter cycle, and, therefore, the LUPD feature must not be used with the PER register.

Re-trigger in RAMP2 operations (RAMP2, RAMP2A, RAMP2C) is not supported if a prescaler is used (CTRLA.PRESCALER != 0) and the re-trig of the counter is done on the next GCLK (CTRLA.PRESCSYNC = GCLK or CTRLA.PRESCSYNC = RESYNC).

If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted.

Using the TCC in the Dithering mode with external retrigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses.

The TCC peripheral is not compatible with an EVSYS channel in the SYNC or RESYNC mode.

The TCC0/TCC1 output is not working as expected with PPS; output signals are not visible on output pins via PPS even though the TCC is working correctly. TCC2 cannot be used to drive external pins.

TCC Overflow (OVF) will not trigger a DMA request in the One-shot DMA trigger (DMAOS) mode of RAMP2C operation.

DMA triggers are not applicable for the RAMP2C mode.

When clearing the STATUS.PERBUFV/STATUS.CCBUFx flag, the SYNCBUSY flag is released before the PERBUF/CCBUFx register is restored to its appropriate value.

In the 8-bit mode, the PER register updates using the DMA are not possible in the Standby mode.

The TC0/1/2/3 output is not working as expected with PPS; output signals are not visible on output pins via PPS even though the TC is working correctly.

ALOCK feature is not functional.

When the interval between clearing the watchdog timer (in other words, clearing the Run mode watchdog counter) and the sleep instruction is less than 1 WDT clock cycle, the “Run Mode” watchdog counter is not cleared. When using LPRC as clock source, the interval is 1 LPRC clock. Because the watchdog timer is in LPRC domain, which is much slower than CPU clock, the sleep instruction is executed even before the “Run mode” watchdog counter is cleared. Hence, the “Run mode” watchdog counter remains frozen to its last count instead of clearing to 0.

While in Sleep mode, the “Sleep mode” watchdog counter is incrementing, and at the end of the WDTPS, it generates an NMI which causes the CPU to wake-up.

After wake-up, the user would expect that, because they cleared the WDT just before going to sleep, they have an entire WDT period available to them before they have to clear WDT again. But because the “Run mode” counter was not cleared before going into sleep, the WDT reset occurs earlier than expected.