24.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 3130292827262524 
  DORDCPOLCMODEFORM[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
   RXPO[1:0]   TXPO 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
        IBON 
Access R 
Reset 0 
Bit 76543210 
 RUNSTDBY  MODE[2:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 30 – DORD Data Order

This bit selects the data order when a character is shifted out from the Data register.

This bit is not synchronized.

ValueDescription
0MSB is transmitted first.
1LSB is transmitted first.

Bit 29 – CPOL Clock Polarity

This bit selects the relationship between data output change and data input sampling in synchronous mode.

This bit is not synchronized.

CPOLTxD ChangeRxD Sample
0x0Rising XCK edgeFalling XCK edge
0x1Falling XCK edgeRising XCK edge

Bit 28 – CMODE Communication Mode

This bit selects asynchronous or synchronous communication.

This bit is not synchronized.

ValueDescription
0Asynchronous communication.
1Synchronous communication.

Bits 27:24 – FORM[3:0] Frame Format

These bits define the frame format.

These bits are not synchronized.

FORM[3:0]Description
0x0USART frame
0x1USART frame with parity
0x2-0x0xFReserved

Bits 21:20 – RXPO[1:0] Receive Data Pinout

These bits define the receive data (RxD) pin configuration.

These bits are not synchronized.

RXPO[1:0]NameDescription
0x0PAD[0]SERCOM PAD[0] is used for data reception
0x1PAD[1]SERCOM PAD[1] is used for data reception
0x2PAD[2]SERCOM PAD[2] is used for data reception
0x3PAD[3]SERCOM PAD[3] is used for data reception

Bit 16 – TXPO Transmit Data Pinout

These bits define the transmit data (TxD) and XCK pin configurations.

This bit is not synchronized.

TXPOTxD Pin LocationXCK Pin Location (When Applicable)
0x0SERCOM PAD[0]SERCOM PAD[1]
0x1SERCOM PAD[2]SERCOM PAD[3]

Bit 8 – IBON Immediate Buffer Overflow Notification

This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.

ValueDescription
0STATUS.BUFOVF is asserted when it occurs in the data stream.
1STATUS.BUFOVF is asserted immediately upon buffer overflow.

Bit 7 – RUNSTDBY Run In Standby

This bit defines the functionality in standby sleep mode.

This bit is not synchronized.

RUNSTDBYExternal ClockInternal Clock
0x0External clock is disconnected when ongoing transfer is finished. All reception is dropped.Generic clock is disabled when ongoing transfer is finished. The device can wake up on Receive Start or Transfer Complete interrupt.
0x1Wake on Receive Start or Receive Complete interrupt.Generic clock is enabled in all sleep modes. Any interrupt can wake up the device.

Bits 4:2 – MODE[2:0] Operating Mode

These bits select the USART serial communication interface of the SERCOM.

These bits are not synchronized.

ValueDescription
0x0USART with external clock
0x1USART with internal clock

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0The peripheral is disabled or being disabled.
1The peripheral is enabled or being enabled.

Bit 0 – SWRST Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

This bit is not enable-protected.

ValueDescription
0There is no reset operation ongoing.
1The reset operation is ongoing.