14.8.4 Generic Clock Generator Control

Name: GENCTRL
Offset: 0x4
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   RUNSTDBYDIVSELOEOOVIDCGENEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
    SRC[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
     ID[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 21 – RUNSTDBY Run in Standby

This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if a peripheral requires the clock.

ValueDescription
0The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be dependent on the setting in GENCTRL.OOV.
1The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby mode.

Bit 20 – DIVSEL Divide Selection

This bit is used to decide how the clock source used by the generic clock generator will be divided. If the clock source should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the corresponding generic clock generator must be zero or one.

ValueDescription
0The generic clock generator equals the clock source divided by GENDIV.DIV.
1The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1).

Bit 19 – OE Output Enable

This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit group.

ValueDescription
0The generic clock generator is not output.
1The generic clock generator is output to the corresponding GCLK_IO, unless the corresponding GCLK_IO is selected as a source in the GENCLK.SRC bit group.

Bit 18 – OOV Output Off Value

This bit is used to control the value of GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit group.

ValueDescription
0The GCLK_IO will be zero when the generic clock generator is turned off or when the OE bit is zero.
1The GCLK_IO will be one when the generic clock generator is turned off or when the OE bit is zero.

Bit 17 – IDC Improve Duty Cycle

This bit is used to improve the duty cycle of the generic clock generator when odd division factors are used.

ValueDescription
0The generic clock generator duty cycle is not 50/50 for odd division factors.
1The generic clock generator duty cycle is 50/50.

Bit 16 – GENEN Generic Clock Generator Enable

This bit is used to enable and disable the generic clock generator.

ValueDescription
0The generic clock generator is disabled.
1The generic clock generator is enabled.

Bits 12:8 – SRC[4:0] Source Select

These bits define the clock source to be used as the source for the generic clock generator, as shown in the table below.

ValueNameDescription
0x00XOSCXOSC oscillator output
0x01GCLKINGenerator input pad
0x02GCLKGEN1Generic clock generator 1 output
0x03OSCULP32KOSCULP32K oscillator output
0x04OSC32KOSC32K oscillator output
0x05XOSC32KXOSC32K oscillator output
0x06OSC8MOSC8M oscillator output
0x07DFLL48MDFLL48M output
0x08-0x1FReservedReserved for future use

Bits 3:0 – ID[3:0] Generic Clock Generator Selection

These bits select the generic clock generator that will be configured or read. The value of the ID bit group versus which generic clock generator is configured is shown in the next table.

A power reset will reset the GENCTRL register for all IDs, including the generic clock generator used by the RTC. If a generic clock generator ID other than generic clock generator 0 is not a source of a “locked” generic clock or a source of the RTC generic clock, a user reset will reset the GENCTRL for this ID.

ValuesNamesDescription
0x0GCLKGEN0Generic clock generator 0
0x1GCLKGEN0Generic clock generator 0
0x2GCLKGEN0Generic clock generator 0
0x3GCLKGEN0Generic clock generator 0
0x4GCLKGEN0Generic clock generator 0
0x5GCLKGEN0Generic clock generator 0
0x6GCLKGEN0Generic clock generator 0
0x7GCLKGEN0Generic clock generator 0
0x8-0xF-Reserved for future use

After a power reset, the reset value of the GENCTRL register is as shown in the next table.

GCLK Generator IDReset Value after a Power Reset
0x000x00010600
0x010x00000001
0x020x00010302
0x030x00000003
0x040x00000004
0x050x00000005
0x060x00000006
0x070x00000007

After a user reset, the reset value of the GENCTRL register is as shown in the table below.

GCLK Generator IDReset Value after a User Reset
0x000x00010600
0x010x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x020x00010302 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x030x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x040x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x050x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x060x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x070x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one