27.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized bits, Enable-Protected bits

Bit 15141312111098 
   PRESCSYNC[1:0]RUNSTDBYPRESCALER[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
  WAVEGEN[1:0] MODE[1:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 13:12 – PRESCSYNC[1:0] Prescaler and Counter Synchronization

These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler.

These bits are not write-synchronized, but are enable-protected.

ValueNameDescription
0x0GCLKReload or reset the counter on next generic clock
0x1PRESCReload or reset the counter on next prescaler clock
0x2RESYNCReload or reset the counter on next generic clock. Reset the prescaler counter
0x3-Reserved

Bit 11 – RUNSTDBY Run in Standby

This bit is used to keep the TC running in Standby mode.

This bit is not write-synchronized, but is enable-protected.

ValueDescription
0The TC is halted in standby.
1The TC continues to run in standby.

Bits 10:8 – PRESCALER[2:0] Prescaler

These bits select the counter prescaler factor.

These bits are not write-synchronized, but are enable protected.

ValueNameDescription
0x0DIV1Prescaler: GCLK_TC
0x1DIV2Prescaler: GCLK_TC/2
0x2DIV4Prescaler: GCLK_TC/4
0x3DIV8Prescaler: GCLK_TC/8
0x4DIV16Prescaler: GCLK_TC/16
0x5DIV64Prescaler: GCLK_TC/64
0x6DIV256Prescaler: GCLK_TC/256
0x7DIV1024Prescaler: GCLK_TC/1024

Bits 6:5 – WAVEGEN[1:0] Waveform Generation Operation

These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output Operations”. It also controls whether frequency or PWM waveform generation should be used. How these modes differ can also be seen from “Waveform Output Operations”.

These bits are not write-synchronized, but are enable-protected.

Table 27-3. Waveform Generation Operation
ValueNameOperationTop ValueWaveform Output on MatchWaveform Output on Wraparound
0x0NFRQNormal frequencyPER(1)/MaxToggleNo action
0x1MFRQMatch frequencyCC0ToggleNo action
0x2NPWMNormal PWMPER(1)/MaxClear when counting up Set when counting downSet when counting up Clear when counting down
0x3MPWMMatch PWMCC0Clear when counting up Set when counting downSet when counting up Clear when counting down
Note:
  1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16-bit and 32-bit modes it is the maximum value.

Bits 3:2 – MODE[1:0] Timer Counter Mode

These bits select the Counter mode.

These bits are not write-synchronized, but are enable protected.

ValueNameDescription
0x0COUNT16Counter in 16-bit mode
0x1COUNT8Counter in 8-bit mode
0x2COUNT32Counter in 32-bit mode
0x3-Reserved

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

This bit is not enable protected.

ValueDescription
0The peripheral is disabled.
1The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

This bit is not enable protected.

ValueDescription
0There is no reset operation ongoing.
1The reset operation is ongoing.