18.8.1 Control - MODE0

Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected, Write-Synchronized

Bit 15141312111098 
     PRESCALER[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 MATCHCLR   MODE[1:0]ENABLESWRST 
Access R/WR/WR/WR/WW 
Reset 00000 

Bits 11:8 – PRESCALER[3:0] Prescaler

These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT).

These bits are not synchronized.

PRESCALER[3:0]NameDescription
0x0DIV1CLK_RTC_CNT = GCLK_RTC/1
0x1DIV2CLK_RTC_CNT = GCLK_RTC/2
0x2DIV4CLK_RTC_CNT = GCLK_RTC/4
0x3DIV8CLK_RTC_CNT = GCLK_RTC/8
0x4DIV16CLK_RTC_CNT = GCLK_RTC/16
0x5DIV32CLK_RTC_CNT = GCLK_RTC/32
0x6DIV64CLK_RTC_CNT = GCLK_RTC/64
0x7DIV128CLK_RTC_CNT = GCLK_RTC/128
0x8DIV256CLK_RTC_CNT = GCLK_RTC/256
0x9DIV512CLK_RTC_CNT = GCLK_RTC/512
0xADIV1024CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xFReserved

Bit 7 – MATCHCLR Clear on Match

This bit is valid only in Mode 0 and Mode 2.

This bit is not synchronized.

ValueDescription
0The counter is not cleared on a Compare/Alarm 0 match.
1The counter is cleared on a Compare/Alarm 0 match.

Bits 3:2 – MODE[1:0] Operating Mode

These bits define the operating mode of the RTC.

These bits are not synchronized.

MODE[1:0]NameDescription
0x0COUNT32Mode 0: 32-bit Counter
0x1COUNT16Mode 1: 16-bit Counter
0x2CLOCKMode 2: Clock/Calendar
0x3Reserved

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0The peripheral is disabled or being disabled.
1The peripheral is enabled or being enabled.

Bit 0 – SWRST Software Reset

Writing a zero to this bit has no effect.

Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled.

Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.

This bit is not enable-protected.

ValueDescription
0There is no reset operation ongoing.
1The reset operation is ongoing.