4.4 Free-Running Mode

In Free-Running mode, a new conversion is started as soon as the previous conversion has completed.

It is configured by writing the Free-Running (FREERUN) bit to ‘1’ in the Control F (ADCn.CTRLF) register as shown in the code snippet below.

ADC0.CTRLF = ADC_FREERUN_bm; /* ADC Free-Running mode enabled */

A new conversion is started immediately after a result is available in the Result (ADCn.RESULT) register. This is signaled by RESRDY in the Interrupt Flags (ADCn.INTFLAGS) register. The Free-Running conversion rate in Single 12-bit is given by:

f conv = f CLK_ADC SAMPDUR + 15.5

For example, given SAMPDUR = 2 and fCLK_ADC = 3.33 MHz, the conversion rate is 188.571 kHz.

The Free-Running conversion rate in single 8-bit is given by:

f conv = f CLK_ADC SAMPDUR + 11.5

For example, given SAMPDUR = 2 and fCLK_ADC = 3.33 MHz, the conversion rate is 246.666 kHz.