5.2 Left Adjust

The Left Adjust (LEFTADJ) bit in the Control F (ADCn.CTRLF) register enables left-shift of the output data in the modes where this is supported. If enabled, this will left-shift the output from both the Result and the Sample registers. It is configured as shown in the following code snippet.

ADC0.CTRLF = ADC_LEFTADJ_bm; /* Enable Left Adjust bit */

Left adjust is available in ADC mode 1, Single Conversion 12-bit.

The following tables show how the left adjust feature affects the Result register output format in Single-Ended and Differential modes.

Table 5-1. RESULT Register – Single-Ended Mode – ADC Mode 1 (Single conversion 12-bit)
LEFTADJRES[31:24]RES[23:16]RES[15:12]RES[11:8]RES[7:0]
00x00Conversion[11:0]
10x00Conversion[11:0] << 4
Table 5-2. RESULT Register – Differential Mode – ADC Mode 1 (Single conversion 12-bit)
LEFTADJRES[31:24]RES[23:16]RES[15:12]RES[11:8]RES[7:0]
0Sign extensionSigned conversion[11:0]
1Sign extensionSigned conversion[11:0] << 4

The following table shows how the left adjust feature affects the Sample register output format in Single-Ended and Differential modes.

Table 5-3. SAMPLE Register – Single-Ended/Differential Mode – ADC Mode 1 (Single conversion 12-bit)
LEFTADJDIFFSAMPLE[15:12]SAMPLE[11:8]SAMPLE[7:0]
000x00Conversion[11:0]
1Sign extensionSigned conversion[11:0]
10Conversion[11:0] << 4
1Signed conversion[11:0] << 4

For example, if the Left Adjust feature is disabled and the ADCn.SAMPLE value is 0x0FFF, the corresponding ADCn.SAMPLE value when Left Adjust is enabled is 0xFFF0.