4 Electrical Specifications

Refer to the device-specific data sheet for the absolute maximum ratings.

Table 4-1. AC/DC Characteristic Timing Requirements for Program/Verify Mode
AC/DC Characteristics		Standard Operating Conditions Production tested at +25°C
Sym.	Characteristics	Min.	Typ.	Max.	Units	Conditions/Comments
Programming Supply Voltages and Currents
V_DD	Supply Voltage (V_DDMIN, V_DDMAX)	1.80	—	5.50	V	(Note 1)
V_PEW	Read/Write and Row Erase Operations	V_DDMIN	—	V_DDMAX	V
V_BE	Bulk Erase Operations	V_BORMAX	—	V_DDMAX	V	(Note 2)
I_DDI	Current on V_DD, Idle	—	—	1.0	mA
I_DDP	Current on V_DD, Programming	—	—	10	mA
I_PP	V_PP
I_PP	Current on MCLR/V_PP	—	—	600	µA
V_IHH	High Voltage on MCLR/V_PP for Program/Verify Mode Entry	7.9	—	9.0	V
T_VHHR	MCLR Rise Time (V_IL to V_IHH) for Program/Verify Mode Entry	—	—	1.0	µs
V_IH	I/O Pins
V_IH	(ICSPCLK, ICSPDAT, MCLR/V_PP) Input High Level	0.8 V_DD	—	V_DD	V
V_IL	(ICSPCLK, ICSPDAT, MCLR/V_PP) Input Low Level	V_SS	—	0.2 V_DD	V
V_OH	ICSPDAT Output High Level	V_DD-0.7	—	—	V	I_OH = 3 mA, V_DD = 3.0V
V_OL	ICSPDAT Output Low Level	—	—	V_SS + 0.6	V	I_OL = 6 mA, V_DD = 3.0V
Programming Mode Entry and Exit
T_ENTS	Programing Mode Entry Setup Time: ICSPCLK, ICSPDAT Setup Time before V_DD or MCLR↑	100	—	—	ns
T_ENTH	Programing Mode Entry Hold Time: ICSPCLK, ICSPDAT Hold Time before V_DD or MCLR↑	250	—	—	μs
Serial Program/Verify
T_CKL	Clock Low Pulse Width	100	—	—	ns
T_CKH	Clock High Pulse Width	100	—	—	ns
T_DS	Data in Setup Time before Clock↓	100	—	—	ns
T_DH	Data in Hold Time after Clock↓	100	—	—	ns
T_CO	Clock↑ to Data Out Valid (during a Read Data from NVM command)	0	—	80	ns
T_LZD	Clock↓ to Data Low-Impedance (during a Read Data from NVM command)	0	—	80	ns
T_HZD	Clock↓ to Data High-Impedance (during a Read Data from NVM command)	0	—	80	ns
T_DLY	Data Input not Driven to Next Clock Input (delay required between command/data or command/command)	1.0	—	—	µs
T_ERAB	Bulk Erase Cycle Time	—	—	13.0	ms	Program, CONFIG, and ID
T_ERAR	Row Erase Cycle Time	—	—	2.8	ms
T_PINT	Internally Timed Programming Operation Time	—	—	2.8	ms	Program Memory
T_PINT	Internally Timed Programming Operation Time	—	—	5.6	ms	Configuration Words
T_PEXT	Delay Required between Begin Externally Timed Programming and End Externally Timed Programming Commands	1.0	—	2.1	ms	(Note 3)
T_DIS	Delay Required after End Externally Timed Programming Command	300	—	—	µs
T_EXIT	Time Delay when Exiting Program/Verify Mode	1	—	—	µs
Note: Bulk Erased devices default to Brown-out Reset enabled with BORV = `1` (low trip point). V_DDMIN is the V_BOR threshold (with BORV = `1`) when performing Low-Voltage Programming on a Bulk Erased device to ensure that the device is not held in Brown-out Reset. The hardware requires V_DD to be above the BOR threshold in order to perform Bulk Erase operations. This threshold does not depend on the BORV Configuration bit setting. Refer to the microcontroller device data sheet specifications for min./typ./max limits of the V_BOR level. Externally timed writes are not supported for Configuration Words.