Pin Allocation Tables

Table . 8-Pin Allocation Table
I/O	8-Pin PDIP SOIC DFN	ADC	Reference	Comparator	ZCD	Timers	CCP/PWM	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	7	ANA0	DAC1OUT1	C1IN0+	—	T3CKI⁽¹⁾ T3G⁽¹⁾ T4IN⁽¹⁾	—	—	CLCIN3⁽¹⁾	SCL2^(1,3,4) SCK2^(1,3,4) SDA2^(1,3,4) SDI2^(1,3,4) SS2^(1,4)	CK1^(1,3) CK2^(1,3,4)	IOCA0	—	ICSPDAT ICDDAT
RA1	6	ANA1	V_REF+ (ADC) DAC1REF0+	C1IN0-	—	T6IN⁽¹⁾	—	—	CLCIN2⁽¹⁾	SCL1^(1,3) SCK1^(1,3)	RX1⁽¹⁾ DT1^(1,3) RX2^(1,4) DT2^(1,3,4)	IOCA1	—	ICSPCLK ICDCLK
RA2	5	ANA2	DAC1REF0-	—	ZCD1	T0CKI⁽¹⁾	—	CWG1^(1,4)	—	SDA1^(1,3) SDI1^(1,3)	—	IOCA2	INT⁽¹⁾	—
RA3	4	—	—	—	—	—	—	—	CLCIN0 ⁽¹⁾	SS1⁽¹⁾	—	IOCA3	—	MCLR V_PP
RA4	3	ANA4	—	C1IN1-	—	T1G⁽¹⁾	—	—	—	—	—	IOCA4	—	CLKOUT SOSCO
RA5	2	ANA5 ADACT⁽¹⁾	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	CCP1⁽¹⁾ CCP2⁽¹⁾	—	CLCIN1⁽¹⁾	—	—	IOCA5	—	CLKIN SOSCI
V_DD	1	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	8	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CWG1A⁽⁴⁾ CWG1B⁽⁴⁾ CWG1C⁽⁴⁾ CWG1D⁽⁴⁾	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2⁽⁴⁾ SCK2⁽⁴⁾ SDA2⁽⁴⁾ SDO2⁽⁴⁾	TX1 DT1 CK1 TX2⁽⁴⁾ DT2⁽⁴⁾ CK2⁽⁴⁾	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. Only available on the 8-pin PIC16F18015.

Table . 14/16-Pin Allocation Table
I/O	14-Pin PDIP SOIC TSSOP	16-Pin VQFN	ADC	Reference	Comparator	ZCD	Timers	CCP	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	13	12	ANA0	DAC1OUT1	C1IN0+	—	—	—	—	—	SS2⁽¹⁾	—	IOCA0	—	ICSPDAT ICDDAT
RA1	12	11	ANA1	V_REF+(ADC) DAC1REF0+	C1IN0-	—	—	—	—	—	—	—	IOCA1	—	ICSPCLK ICDCLK
RA2	11	10	ANA2	DAC1REF0-	—	ZCD1	T0CKI⁽¹⁾	—	CWG1⁽¹⁾	—	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	3	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	2	ANA4	—	—	—	T1G⁽¹⁾	—	—	—	—	—	IOCA4	—	CLKOUT SOSCO
RA5	2	1	ANA5	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	—	CLCIN3⁽¹⁾	—	—	IOCA5	—	CLKIN SOSCI
RC0	10	9	ANC0	—	—	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	CK2^(1,3)	IOCC0	—	—
RC1	9	8	ANC1	—	C1IN1-	—	T4IN ⁽¹⁾	—	—	CLCIN2⁽¹⁾	SDA1^(1,3,4) SDI1^(1,3,4)	RX2⁽¹⁾ DT2^(1,3)	IOCC1	—	—
RC2	8	7	ANC2 ADACT⁽¹⁾	—	C1IN2-	—	T6IN ⁽¹⁾	—	—	—	—	—	IOCC2	—	—
RC3	7	6	ANC3	—	C1IN3-	—	—	CCP2⁽¹⁾	—	CLCIN0⁽¹⁾	SS1⁽¹⁾	—	IOCC3	—	—
RC4	6	5	ANC4	—	—	—	T3G⁽¹⁾	—	—	CLCIN1⁽¹⁾	SCL2^(1,3,4) SCK2^(1,3,4)	CK1^(1,3)	IOCC4	—	—
RC5	5	4	ANC5	—	—	—	T3CKI⁽¹⁾	CCP1⁽¹⁾	—	—	SDA2^(1,3,4) SDI2^(1,3,4)	RX1⁽¹⁾ DT1^(1,3)	IOCC5	—	—
V_DD	1	16	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	14	13	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table . 20-Pin Allocation Table
I/O	20-Pin PDIP SOIC SSOP	20-Pin QFN	ADC	Reference	Comparator	ZCD	Timers	CCP	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	19	16	ANA0	DAC1OUT1	C1IN0+	—	—	—	—	—	—	—	IOCA0	—	ICSPDAT ICDDAT
RA1	18	15	ANA1	V_REF+(ADC) DAC1REF0+	C1IN0-	—	—	—	—	—	SS2⁽¹⁾	—	IOCA1	—	ICSPCLK ICDCLK
RA2	17	14	ANA2	DAC1REF0-	—	ZCD1	T0CKI⁽¹⁾	—	CWG1⁽¹⁾	CLCIN0⁽¹⁾	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	1	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	20	ANA4	—	—	—	T1G⁽¹⁾	—	—	—	—	—	IOCA4	—	CLKOUT SOSCO
RA5	2	19	ANA5	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	—	—	—	—	IOCA5	—	CLKIN SOSCI
RB4	13	10	ANB4	—	—	—	—	—	—	CLCIN2⁽¹⁾	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCB4	—	—
RB5	12	9	ANB5	—	—	—	—	—	—	CLCIN3⁽¹⁾	SDA2^(1,3,4) SDI2^(1,3,4)	RX1⁽¹⁾ DT1^(1,3)	IOCB5	—	—
RB6	11	8	ANB6	—	—	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCB6	—	—
RB7	10	7	ANB7	—	—	—	—	—	—	—	SCL2^(1,3,4) SCK2^(1,3,4)	CK1^(1,3)	IOCB7	—	—
RC0	16	13	ANC0	—	—	—	—	—	—	—	—	CK2^(1,3)	IOCC0	—	—
RC1	15	12	ANC1	—	C1IN1-	—	T4IN⁽¹⁾	—	—	—	—	RX2⁽¹⁾ DT2^(1,3)	IOCC1	—	—
RC2	14	11	ANC2 ADACT⁽¹⁾	—	C1IN2-	—	T6IN⁽¹⁾	—	—	—	—	—	IOCC2	—	—
RC3	7	4	ANC3	—	C1IN3-	—	—	CCP2⁽¹⁾	—	CLCIN1⁽¹⁾	—	—	IOCC3	—	—
RC4	6	3	ANC4	—	—	—	T3G⁽¹⁾	—	—	—	—	—	IOCC4	—	—
RC5	5	2	ANC5	—	—	—	T3CKI⁽¹⁾	CCP1⁽¹⁾	—	—	—	—	IOCC5	—	—
RC6	8	5	ANC6	—	—	—	—	—	—	—	SS1⁽¹⁾	—	IOCC6	—	—
RC7	9	6	ANC7	—	—	—	—	—	—	—	—	—	IOCC7	—	—
V_DD	1	18	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	20	17	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table . 28-Pin Allocation Table
I/O	28-Pin SPDIP SOIC SSOP	28-Pin VQFN	ADC	Reference	Comparator	ZCD	Timers	CCP	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	2	27	ANA0	—	C1IN0-	—	—	—	—	CLCIN0⁽¹⁾	—	—	IOCA0	—	—
RA1	3	28	ANA1	—	C1IN1-	—	—	—	—	CLCIN1⁽¹⁾	—	—	IOCA1	—	—
RA2	4	1	ANA2	DAC1REF0-	C1IN0+	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	2	ANA3	DAC1REF0+ V_REF+ (ADC)	C1IN1+	—	—	—	—	—	—	—	IOCA3	—	—
RA4	6	3	ANA4	—	—	—	T0CKI⁽¹⁾	—	—	—	—	—	IOCA4	—	—
RA5	7	4	ANA5	—	—	—	—	—	—	—	SS1⁽¹⁾	—	IOCA5	—	—
RA6	10	7	ANA6	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT
RA7	9	6	ANA7	—	—	—	—	—	—	—	—	—	IOCA7	—	CLKIN
RB0	21	18	ANB0	—	—	ZCD1	—	—	CWG1⁽¹⁾	—	SS2	—	IOCB0	INT⁽¹⁾	—
RB1	22	19	ANB1	—	C1IN3-	—	—	—	—	—	SCL2^(1,3,4) SCK2^(1,3,4)	—	IOCB1	—	—
RB2	23	20	ANB2	—	—	—	—	—	—	—	SDA2^(1,3,4) SDI2^(1,3,4)	—	IOCB2	—	—
RB3	24	21	ANB3	—	C1IN2-	—	—	—	—	—	—	—	IOCB3	—	—
RB4	25	22	ANB4 ADACT⁽¹⁾	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	26	23	ANB5	—	—	—	T1G⁽¹⁾	—	—	—	—	—	IOCB5	—	—
RB6	27	24	ANB6	—	—	—	—	—	—	CLCIN2⁽¹⁾	—	CK2^(1,3)	IOCB6	—	ICSPCLK ICDCLK
RB7	28	25	ANB7	DAC1OUT2	—	—	T6IN⁽¹⁾	—	—	CLCIN3⁽¹⁾	—	RX2⁽¹⁾ DT2^(1,3)	IOCB7	—	ICSPDAT ICDDAT
RC0	11	8	ANC0	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾	—	—	—	—	—	IOCC0	—	SOSCO
RC1	12	9	ANC1	—	—	—	—	CCP2⁽¹⁾	—	—	—	—	IOCC1	—	SOSCI
RC2	13	10	ANC2	—	—	—	—	CCP1⁽¹⁾	—	—	—	—	IOCC2	—	—
RC3	14	11	ANC3	—	—	—	T2IN⁽¹⁾	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCC3	—	—
RC4	15	12	ANC4	—	—	—	—	—	—	—	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCC4	—	—
RC5	16	13	ANC5	—	—	—	T4IN⁽¹⁾	—	—	—	—	—	IOCC5	—	—
RC6	17	14	ANC6	—	—	—	—	—	—	—	—	CK1^(1,3)	IOCC6	—	—
RC7	18	15	ANC7	—	—	—	—	—	—	—	—	RX1⁽¹⁾ DT1^(1,3)	IOCC7	—	—
RE3	1	26	—	—	—	—	—	—	—	—	—	—	IOCE3	—	MCLR V_PP
V_DD	20	17	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	8 19	5 16	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table . 40/44-Pin Allocation Table
I/O	40-Pin PDIP	40-Pin QFN	44-Pin TQFP	ADC	Reference	Comparator	ZCD	Timers	CCP	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	2	17	19	ANA0	—	C1IN0-	—	—	—	—	CLCIN0⁽¹⁾	—	—	IOCA0	—	—
RA1	3	18	20	ANA1	—	C1IN1-	—	—	—	—	CLCIN1⁽¹⁾	—	—	IOCA1	—	—
RA2	4	19	21	ANA2	DAC1REF0-	C1IN0+	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	20	22	ANA3	DAC1REF0+ V_REF+ (ADC)	C1IN1+	—	—	—	—	—	—	—	IOCA3	—	—
RA4	6	21	23	ANA4	—	—	—	T0CKI⁽¹⁾	—	—	—	—	—	IOCA4	—	—
RA5	7	22	24	ANA5	—	—	—	—	—	—	—	SS1⁽¹⁾	—	IOCA5	—	—
RA6	14	29	31	ANA6	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT
RA7	13	28	30	ANA7	—	—	—	—	—	—	—	—	—	IOCA7	—	CLKIN
RB0	33	8	8	ANB0	—	—	ZCD1	—	—	CWG1⁽¹⁾	—	SS2⁽¹⁾	—	IOCB0	INT⁽¹⁾	—
RB1	34	9	9	ANB1	—	C1IN3-	—	—	—	—	—	SCL2^(1,3,4) SCK2^(1,3,4)	—	IOCB1	—	—
RB2	35	10	10	ANB2	—	—	—	—	—	—	—	SDA2^(1,3,4) SDI2^(1,3,4)	—	IOCB2	—	—
RB3	36	11	11	ANB3	—	C1IN2-	—	—	—	—	—	—	—	IOCB3	—	—
RB4	37	12	14	ANB4 ADACT⁽¹⁾	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	38	13	15	ANB5	—	—	—	T1G⁽¹⁾	—	—	—	—	—	IOCB5	—	—
RB6	39	14	16	ANB6	—	—	—	—	—	—	CLCIN2⁽¹⁾	—	CK2^(1,3)	IOCB6	—	ICSPCLK ICDCLK
RB7	40	15	17	ANB7	DAC1OUT2	—	—	T6IN⁽¹⁾	—	—	CLCIN3⁽¹⁾	—	RX2⁽¹⁾ DT2^(1,3)	IOCB7	—	ICSPDAT ICDDAT
RC0	15	30	32	ANC0	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾	—	—	—	—	—	IOCC0	—	SOSCO
RC1	16	31	35	ANC1	—	—	—	—	CCP2⁽¹⁾	—	—	—	—	IOCC1	—	SOSCI
RC2	17	32	36	ANP2	—	—	—	—	CCP1⁽¹⁾	—	—	—	—	IOCC2	—	—
RC3	18	33	37	ANC3	—	—	—	T2IN⁽¹⁾	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCC3	—	—
RC4	23	38	42	ANC4	—	—	—	—	—	—	—	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCC4	—	—
RC5	24	39	43	ANC5	—	—	—	T4IN⁽¹⁾	—	—	—	—	—	IOCC5	—	—
RC6	25	40	44	ANC6	—	—	—	—	—	—	—	—	CK1^(1,3)	IOCC6	—	—
RC7	26	1	1	ANC7	—	—	—	—	—	—	—	—	RX1⁽¹⁾ DT1^(1,3)	IOCC7	—	—
RD0	19	34	38	AND0	—	—	—	—	—	—	—	—	—	—	—	—
RD1	20	35	39	AND1	—	—	—	—	—	—	—	—	—	—	—	—
RD2	21	36	40	AND2	—	—	—	—	—	—	—	—	—	—	—	—
RD3	22	37	41	AND3	—	—	—	—	—	—	—	—	—	—	—	—
RD4	27	2	2	AND4	—	—	—	—	—	—	—	—	—	—	—	—
RD5	28	3	3	AND5	—	—	—	—	—	—	—	—	—	—	—	—
RD6	29	4	4	AND6	—	—	—	—	—	—	—	—	—	—	—	—
RD7	30	5	5	AND7	—	—	—	—	—	—	—	—	—	—	—	—
RE0	8	23	25	ANE0	—	—	—	—	—	—	—	—	—	IOCE0	—	—
RE1	9	24	26	ANE1	—	—	—	—	—	—	—	—	—	IOCE1	—	—
RE2	10	25	27	ANE2	—	—	—	—	—	—	—	—	—	IOCE2	—	—
RE3	1	16	18	—	—	—	—	—	—	—	—	—	—	IOCE3	—	MCLR V_PP
V_DD	11 32	7 26	7 28	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	12 31	6 27	6 29	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2 PWM3 PWM4 PWM5	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

PIC16F180XX

Pin Allocation Tables