3.3 AC Parameters: All I/O Interfaces

Figure 3-1. Wake Timing: All Interfaces

Table 3-2. AC Parameters: All I/O Interfaces
Parameter	Sym.	Direction	Min.	Typ.	Max.	Units	Conditions
Power-Up Delay	t_PU	To Crypto Device	100	—	—	µs	Minimum time between V_CC > V_CC min prior to start of t_WLO.
Wake Low Duration	t_WLO	To Crypto Device	60	—	—	µs	—
Initialization Time⁽¹⁾	t_{DVC_INIT}	Internal	—	—	400	µs	Maximum time from rising edge of wake pulse until device is initialized.⁽²⁾
Wake High Delay to Data Comm	t_WHI	To Crypto Device	1500	—	—	µs	SDA is recommended to be stable high for this entire duration unless polling is implemented. SelfTest is not enabled at power-up.
Wake High Delay when SelfTest is Enabled	t_WHIST	To Crypto Device	20	—	—	ms	SDA is recommended to be stable high for this entire duration unless polling is implemented.
High-Side Glitch Filter at Active⁽¹⁾	t_{HIGNORE_A}	To Crypto Device	45	—	—	ns	Pulses shorter than this in width will be ignored by the device, regardless of its state when active.
Low-Side Glitch Filter at Active⁽¹⁾	t_{LIGNORE_A}	To Crypto Device	45	—	—	ns	Pulses shorter than this in width will be ignored by the device, regardless of its state when active.
Low-Side Glitch Filter at Sleep⁽¹⁾	t_{LIGNORE_S}	To Crypto Device	15	—	—	µs	Pulses shorter than this in width will be ignored by the device when in Sleep mode.
Watchdog Time-out	t_WATCHDOG	To Crypto Device	0.7	1.3	1.7	s	Time from wake until device is forced into Sleep mode if Config.ChipMode[2] is 0.

Note:

These parameters are characterized, but not production tested.
No communications, other than the wake pulse, on the I²C bus is recommended until after t_{DVC_INIT} time has passed.