7 × 32 Bits EEPROM user memory including 32-bit password memory
2 × 32 Bits unique ID
1 × 32-bit option register in EEPROM to set up the analog front end:
Clock detection level
Gap detection level
Improved downlink timing
Clamp voltage
Modulation voltage
Soft modulation switching
Write damping like the T5557/ATA5567 or with Resistor
Downlink protocol
1 × 32-bit configuration register in EEPROM to set up:
Data rate:
RF/2 to RF/128, binary selectable or
Fixed basic mode rates
Modulation/coding:
ASK, FSK, PSK, Manchester, bi-phase, NRZ
Other options:
Password mode
Max block feature
Direct access mode
Sequence terminator(s)
Block-wise write protection (lock bit)
Answer-on-request (AOR) mode
Inverse data output
Disable test mode access
Fast downlink (~6 Kbits/s vs. ~3 Kbits/s)
OTP functionality
Init delay (~67 ms)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.