23.3.3.4.4 Dual-Slope PWM

For the dual-slope PWM generation, the period (T) is controlled by TCAn.PER, while the values of TCAn.CMPn control the duty cycle of the WG output.

The figure below shows how, for dual-slope PWM, the counter repeatedly counts from BOTTOM to TOP and then from TOP to BOTTOM. The waveform generator output is set at BOTTOM, cleared on compare match when up-counting, and set on compare match when down-counting.

CMPn = BOTTOM produces a static low signal on WOn, while CMPn = TOP produces a static high signal on WOn.

Figure 23-13. Dual-Slope Pulse-Width Modulation
Note: The representation in the figure above is valid when CMPn is updated using CMPnBUF.

The Period (TCAn.PER) register defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER = 0x0003), and the maximum resolution is 16 bits (TCAn.PER = MAX).

The following equation calculates the exact resolution in bits for dual-slope PWM (RPWM_DS):

R PWM_DS = log PER + 1 log 2

The PWM frequency depends on the period setting in the TCAn.PER register, the peripheral clock frequency (fCLK_PER), and the prescaler divider selected in the CLKSEL bit field in the TCAn.CTRLA register. It is calculated by the following equation:

f PWM_DS = f CLK_PER 2 N ⋅ PER

N represents the prescaler divider used.

Using dual-slope PWM results in approximately half the maximum operation frequency compared to single-slope PWM operation, due to twice the number of timer increments per period.