8.8.2.4 System Configuration 0

The default value given in this fuse description is the factory-programmed value and must not be mistaken for the Reset value.

Name:	SYSCFG0
Offset:	0x05
Reset:	0xD0
Property:	-


Bit	7	6	5	4	3	2	1	0
	CRCSRC[1:0]		CRCSEL	UPDIPINCFG	RSTPINCFG			EESAVE
Access	R	R	R	R	R			R
Reset	1	1	0	1	0			0

Bits 7:6 – CRCSRC[1:0] CRC Source

This bit field controls which section of the Flash will be checked by the CRCSCAN peripheral during the Reset initialization. Refer to the CRCSCAN - Cyclic Redundancy Check Memory Scan section for more information about the functionality.

Value	Name	Description
0x0	FLASH	CRC of full Flash (boot, application code, and application data)
0x1	BOOT	CRC of the Boot section
0x2	BOOTAPP	CRC of the Application code and Boot sections
0x3	NOCRC	No CRC

Bit 5 – CRCSEL CRC Mode Selection

This bit controls the type of CRC performed by the CRCSCAN peripheral. Refer to the CRCSCAN - Cyclic Redundancy Check Memory Scan section for more information about the functionality.

Value	Name	Description
0	CRC16	CRC-16-CCITT
1	CRC32	CRC-32 (IEEE 802.3)

Bit 4 – UPDIPINCFG Configuration of UPDI Pin at Start-Up

This bit controls the pin configuration for the UPDI pin.

Value	Name	Description
0	GPIO	UPDI pin is configured as GPIO
1	UPDI	UPDI pin is configured as UPDI pin with pull-up enabled on PF7. This is the factory default value

Bit 3 – RSTPINCFG Reset Pin Configuration at Start-Up

This bit controls the pin configuration of the Reset pin.

Value	Name	Description
0	INPUT	PF6 is configured as a general input pin. This is the factory default value.
1	RESET	External Reset enabled on PF6

Bit 0 – EESAVE EEPROM Save During Chip Erase

This bit controls whether the EEPROM is erased or preserved during a chip erase. If enabled, only the flash memory will be erased by the chip erase.

Value	Name	Description
0	DISABLE	EEPROM is erased during chip erase
1	ENABLE	EEPROM is preserved during a chip erase regardless of whether the device is locked or not