Programming Overview

This document defines the programming specification for the dsPIC33AK256MPS306 Family Digital Signal Controller (DSC) devices:

  • dsPIC33AK128MPS303
  • dsPIC33AK128MPS103
  • dsPIC33AK128MPS305
  • dsPIC33AK128MPS105
  • dsPIC33AK128MPS306
  • dsPIC33AK128MPS106
  • dsPIC33AK256MPS303
  • dsPIC33AK256MPS103
  • dsPIC33AK256MPS305
  • dsPIC33AK256MPS105
  • dsPIC33AK256MPS306
  • dsPIC33AK256MPS106

The programming is implemented via the In-Circuit Serial Programming (ICSP™) interface, which includes the clock and data pins (PGECx and PGEDx).

The dsPIC33AK256MPS306 devices have a Nonvolatile Memory (NVM) controller module. This NVM module performs the device Flash memory programming. Its operation is configured and managed by the CPU. The external programmer tool uses the serial programming interface (ICSP) to shift in and execute CPU instructions, move data in and out of the device, and configure the NVM controller for programming operations. The programmer sends MOV instructions to the CPU to store (prepare) the Flash data to be programmed in the device RAM or NVM Control registers, depending on the Programming mode. Then, the programmer executes CPU instructions to initiate erase or write operations using the NVM controller. To read Flash data from the device, a VISI register is implemented. The content of this register can be shifted out to the ICSP interface. For fast Flash content verification, the NVM controller supports a CRC-32 checksum engine. It can reduce the amount of data which should be read over the ICSP communications pins. Figure explains the interactions between the programmer and the device.

Figure . Programming Interactions Block Diagram