1 Flash Memory

The Flash memory on dsPIC33AK256MPS306 family devices is divided into quadwords (16 bytes each), write rows (512 bytes each) and erase pages (4096 bytes each). The quadword (four 32-bit long words) is the minimum data size that can be written into the Flash. The address of each quadword is aligned by 16 bytes. The Flash memory can be written by rows, and each row consists of 32 quadwords or 512 bytes. The address of each row is aligned by 512-byte boundaries.

The Flash memory must be erased before a write operation can be initiated, and it can be erased by pages. Each erase page consists of eight rows or 4096 bytes. The address of each erase page is aligned by 4096-byte boundaries.

The dsPIC33AK256MPS306 family devices’ Flash memory regions are shown in Table 1-1.

Table 1-1. Flash Memory Map
Memory Region			Address	Number of Quadwords	Number of Write Rows	Number of Erase Pages	Description
User OTP			0x7F2C00-0x7F3000	64	2	Not applicable	Quadword or row programmed, never erasable
User Configuration A (UCA1)			0x7F3000-0x7F3FFC	256	8	1	Bulk or page erased, quadword programmed
User Configuration B (UCB)			0x7F4000-0x7F4FFC	256	8	1
User Configuration A2 (UCA2)			0x7FB000-0x7FBFFC	256	8	1⁽¹⁾
Code Memory	128-Kbyte Flash Memory Devices	Single Boot	800000-81FFFC	8182	256	32	Bulk or page erased, quadword or row programmed
		Dual Boot	800000-80FFFC	4091	128	16
		Dual Boot	C00000-C0FFFC	4091	128	16
	256-Kbyte Flash Memory Devices	Single Boot	800000-83FFFC	16384	512	64
		Dual Boot	800000-81FFFC	8182	256	32
		Dual Boot	C00000-C1FFFC	8182	256	32
Note: UCA2 is used only when the device operates in a Dual Partition Flash mode. In Single Partition mode, only UCA1 is active.

Some dsPIC33AK256MPS306 family device registers are used in the programming procedures. The descriptions and addresses of these registers are listed in Table 1-2.

Table 1-2. Registers Used in the Programming Procedures
Register Name	Address	Description
VISI	0x0007C0	This is a register to move (shift) data out of the device through the ICSP interface.
NVMCON	0x003000	This is a register to select type and initiate erase or write Flash operations.
NVMADR	0x003004	This register is the destination Flash address for erase or write operations.
NVMDATA0	0x003008	This is a register with data to be programmed to Flash when quadword write is used.
NVMDATA1	0x00300C	This is a register with data to be programmed to Flash when quadword write is used.
NVMDATA2	0x003010	This is a register with data to be programmed to Flash when quadword write is used.
NVMDATA3	0x003014	This is a register with data to be programmed to Flash when quadword write is used.
NVMSRCADR	0x003018	This register should be set to the address of the RAM buffer loaded with the Flash row data to be programmed.
NVMCRCCON	0x003048	This register controls the Cyclic Redundancy Check (CRC) calculation of the Flash region.
NVMCRCST	0x00304C	This register contains the start address of the 4-Kbyte Flash memory block for the CRC calculation.
NVMCRCEND	0x003050	This register contains the end address of the 4-Kbyte Flash memory block minus one byte for the CRC calculation.
NVMCRCSEED	0x003054	The initial CRC value (seed) should be loaded into this register. If the CRC-32 is calculated for the multiple memory blocks, then the previous CRC result must be written directly to NVMCRCSEED before the next block of CRC calculations.
NVMCRCDATA	0x003058	This register contains the CRC calculation result.