2.3.1 TWI Data Setup Time Can Be Too Short
When running the device as a TWI slave with a system clock above 2 MHz, the data setup time for the first bit after ACK may, in some cases, be too short. This may cause a false start or stop condition on the TWI line.
Work around
Insert a delay between setting TWDR and TWCR.
Affected Silicon Revisions
| ATmega48A/PA | ||
|---|---|---|
| Rev. D | Rev. E | |
| X | X | |
| ATmega88A/PA | ||
| Rev. F | Rev. G | |
| X | X | |
| ATmega168A/PA | ||
| Rev. E | Rev. L | |
| X | X | |
| ATmega328/P | ||
| Rev. A | Rev. B | Rev. D |
| - | - | X |