1.34.2 Clock Generator (CLOCK)

The Clock system generates and distributes the clock for the processor and peripherals.

Clock Generators:

  • 3 to 20 MHz main crystal oscillator with bypass mode. 12 MHz or 16 MHz needed for USB operations

  • High-precision Main RC oscillator with 12 MHz default frequency

  • Low-power 32.768 kHz crystal oscillator with bypass mode

  • Low-power 32 kHz Slow RC Oscillator (SLCK)

  • 160-500 MHz programmable PLL for system clock

  • 480 MHz UTMI PLL providing clock to USB High-speed controller

Clock Distribution

  • Master clock controller generates Processor Clock (HCLK) and Master Clock (MCK). The master clock (MCK) is the source clock for many peripherals

  • The Peripheral Clock Controller enables and disables clocks to different peripherals running from Master clock

  • Programmable Clock Controller (PCK) provides clock for USART, UART, TC, Embedded Trace Macrocell (ETM), and CAN peripherals. The PCK is independent of the processor clock and the master clock

  • Generic Clock Controller (GCLK) provides clock for I2S peripheral. The GCLK is independent of the processor clock and the master clock

Using The Library

The Clock peripheral library initializes the clock system as configured by the user in the MHC easy view.

Library Interface

Clock Generator peripheral library provides the following interfaces:

Functions

Name Description
CLK_Initialize Initializes hardware of the System Clock and Peripheral Clock