1.32.15 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) supports:

• Tightly coupled interrupt controller provides low interrupt latency

• An implementation-defined number of interrupts, in the range 1-240 interrupts

• A programmable priority level for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.

• Supports Vectored interrupt where each interrupt has its own vector stored in a vector table

• Relocatable Vector table defines the entry address of the processor exceptions and the peripheral interrupts to automatically service the required exception or interrupt

• Non-Maskable Interrupt

• Software interrupt generation

• The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling.

The example code below demonstrates how to Disable global interrupts and then restore based on saved state.

bool intState = NVIC_INT_Disable();

NVIC_INT_Restore(intState);

Using The Library

The NVIC peripheral library initializes interrupt controller as configured by the user in the MHC. The user can enable interrupt, configure priority and specify the interrupt vector name.

Library Interface

Nested Vectored Interrupt Controller peripheral library provides the following interfaces:

Functions

Name	Description
NVIC_Initialize	Initializes interrupt controller (NVIC) module of the device
NVIC_INT_Enable	Enables all global interrupts
NVIC_INT_Disable	Disables all global interrupts and returns PRIMASK bit status
NVIC_INT_Restore	Enables or Disables all global interrupts based on PRIMASK bit state