1.27.21 Static Memory Controller (SMC)

This Static Memory Controller (SMC) is capable of handling several types of external memory and peripheral devices, such as SRAM,

PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.

The SMC generates the signals that control the access to external memory devices or peripheral devices. It has 4 Chip Selects and a 26-

bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control

signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.

The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic Slow

Clock mode. In Slow Clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals.

The SMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles

to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead.

The SMC includes programmable hardware error correcting code with one-bit error correction capability and supports two-bit error detection.

In order to improve the overall system performance, the DATA phase of the transfer can be DMA-assisted.

The External Data Bus can be scrambled/unscrambled by means of user keys.

Using The Library

Static Memory Controller (SMC) is initialized as configured in the MHC as part of System Initialization.

Library Interface

Static Memory Controller peripheral library provides the following interfaces:

Functions

Name	Description
SMC_Initialize	Initializes Static Memory Controller (SMC) interface