29.3.2.7 Clock Source Settings

The Filter, edge detector, and Sequential logic are by default clocked by the system clock (CLK_PER). It is also possible to use the LUT input 2 (IN[2]) to clock these blocks (CLK_MUX_OUT in the figure below). This is configured by writing the Clock Source (CLKSRC) bit in the LUT Control A (CCL.LUTnCTRLA) register to ‘1’.

When the Clock Source (CLKSRC) bit is ‘1’, IN[2] is used to clock the corresponding filter and edge detector (CLK_MUX_OUT). The Sequential logic is clocked by CLK_MUX_OUT of the even LUT in the pair. When the CLKSRC bit is ‘1’, IN[2] is treated as MASKed (low) in the truth table.

The CCL peripheral must be disabled while changing the clock source to avoid undetermined outputs from the peripheral.