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PIC18F27/47/57Q43 Silicon Errata and Data Sheet Clarifications
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PIC18F27Q43
PIC18F47Q43
PIC18F57Q43
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1
Silicon Errata Issues
1.3
Module: Inter-Integrated Circuit (I
2
C)
***
1
Silicon Errata Issues
1.1
Module: Analog-to-Digital Converter with Computation (ADCC)
1.2
Module: Oscillator (OSC)
1.3
Module: Inter-Integrated Circuit (I
2
C)
1.3.1
The I2CxADR0/1/2/3 Registers Have Incorrect Reset Value
1.3.2
The I
2
C Start and/or Stop Flags May Be Set When I
2
C Is Enabled
1.3.3
Operating in Multi-Host Mode Will Cause Bus Failures
1.3.4
MDR Bit Is Not Cleared after Bus Time-Out
1.3.5
Bus Time-Out Not Detected Properly When External Host Clock Stretches
1.3.6
Clock Stretch Disable Not Working Properly
1.3.7
Bus Time-Out Causes False Start/Stop
1.3.8
The Bus Free Divider Ratio BFREDR = 1 Value Is Not Functional
1.3.9
CSTR Bit Is Not Cleared after Bus Time-Out
1.3.10
Bus Collision Followed by a Stop Condition during a Transaction by an External Host Device May Hang the Bus
1.3.11
I
2
C Module May Hang the Bus during Multi-Host Arbitration
1.4
Module: SRAM
1.5
Module: In-Circuit Debug
1.6
Module: Signal Measurement Timer (SMT)
1.7
Module: Universal Asynchronous Receiver Transmitter (UART)
2
Data Sheet Clarifications
3
Appendix A: Revision History
Microchip Information
1.3 Module: Inter-Integrated Circuit (I
2
C)
