28.10.5 TxCLKCON

Timer Clock Source Selection Register

Name:	TxCLKCON
Address:	0x321,0x32E,0x335


Bit	7	6	5	4	3	2	1	0
				CS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CS[4:0] Timer Clock Source Selection

Table 28-3. Clock Source Selection
CS	Clock Source
CS	Timer2	Timer4	Timer6
`11111 - 10100`	Reserved
`10011`	CLC8_OUT
`10010`	CLC7_OUT
`10001`	CLC6_OUT
`10000`	CLC5_OUT
`01111`	CLC4_OUT
`01110`	CLC3_OUT
`01101`	CLC2_OUT
`01100`	CLC1_OUT
`01011`	ZCD_OUT
`01010`	NCO1_OUT
`01001`	CLKREF_OUT
`01000`	EXTOSC
`00111`	SOSC
`00110`	MFINTOSC (31.25 kHz)
`00101`	MFINTOSC (500 kHz)
`00100`	LFINTOSC
`00011`	HFINTOSC
`00010`	F_OSC
`00001`	F_OSC/4
`00000`	Pin selected by T2INPPS	Pin selected by T4INPPS	Pin selected by T6INPPS

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