27.12.3 TxCLK

Timer Clock Source Selection Register
Name: TxCLK
Address: 0x317,0x328

Bit 76543210 
    CS[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 4:0 – CS[4:0] Timer Clock Source Selection

Table 27-4. Timer Clock Sources
CSClock Source
Timer1Timer3
11111 - 10110Reserved
10101CLC8_OUT
10100CLC7_OUT
10011CLC6_OUT
10010CLC5_OUT
10001CLC4_OUT
10000CLC3_OUT
01111CLC2_OUT
01110CLC1_OUT
01101TMR3_OUTReserved
01100ReservedTMR1_OUT
01011TMR0_OUT
01010CLKREF_OUT
01001EXTOSC
01000SFINTOSC
00111SOSC
00110MFINTOSC (31.25 kHz)
00101MFINTOSC (500 kHz)
00100LFINTOSC
00011HFINTOSC
00010FOSC
00001FOSC/4
00000Pin selected by T1CKIPPSPin selected by T3CKIPPS
Reset States: 
POR/BOR = 00000
All Other Resets = uuuuu