3.4.1 Debug JTAG

This section describes the signals and connectors related to the JTAG interface.

A 10-pin JTAG header is provided on the baseboard to facilitate software development and debugging using various JTAG emulators. The interface signals have a voltage level of 3.3V.

Figure 3-34. JTAG Interface

Figure 3-35. JTAG Connector J11 Location

The table below describes the pin assignment of JTAG connector J11.

Table 3-18. JTAG/ICE Connector J11 Pin Assignment
Pin No	Mnemonic	Signal Description
1	VTref. 3.3V power	This is the target reference voltage (main 3.3V).
2	TMS TEST MODE SELECT	JTAG mode set input into target processor
3	GND	Common ground
4	TCK TEST CLOCK - Output timing signal, for synchronizing test logic and control register access	JTAG clock signal into target processor
5	GND	Common ground
6	TDO JTAG TEST DATA OUTPUT - Serial data input from the target	JTAG data output from target processor
7	RTCK - Input return test clock signal from the target	Some targets with a slow system clock must synchronize the JTAG inputs to internal clocks. In the present case, such synchronization is unneeded and TCK is merely looped back into RTCK.
8	TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal	JTAG data input into target processor
9	GND	Common ground
10	nRST RESET	Active-low reset signal. Target processor reset signal.