3.14 I²C - Communication

Interface Bus

The device communicates with the host over an I²C bus. Devices are connected to the I²C bus, as shown in the figure below. Both bus lines are connected to V_DD via pull-up resistors. The bus drivers of all I²C devices must be open-drain type, which implements a wired-AND function that allows all devices to drive the bus, one at a time. A low level on the bus is generated when a device outputs a zero.

General I²C Bus

The I²C provides a simple, bidirectional, two-wire communication bus consisting of:

• Serial Data Line (SDA) for packet transfer
• Serial Clock Line (SCL) for the bus clock

The two lines are open-collector lines (wired-AND).

The I²C bus topology is a simple and efficient method of interconnecting multiple devices on a serial bus. A device connected to the bus can be a host or a client. Only host devices can control the bus and the bus communication. A unique address is assigned to each client device connected to the bus, and the host will use it to control the client and initiate a transaction.

A host indicates the start of a transaction by issuing a Start condition (S) on the bus. The host provides the clock signal for the transaction. An address packet with a 7-bit client address (ADDRESS) and a direction bit, representing whether the host wishes to read or write data (R/W), are then sent.

The addressed I²C client will then acknowledge (ACK) the address, and data packet transactions can begin. Every 9-bit data packet consists of eight data bits followed by a 1-bit reply indicating whether the data were acknowledged by the receiver.

After all the data packets (DATA) are transferred, the host issues a Stop condition (P) on the bus to end the transaction.