3.2.4 I/O Lines Description

Table 3-1. EBI I/O Lines Description
Name	Function	Type	Active Level
EBI
EBI_D[15:0]	Data Bus	I/O	–
EBI_A[22:0]	Address Bus	Output	–
EBI_NWAIT	External Wait Signal	Input	Low
SMC
EBI_NCS[2:0]	Chip Select Lines	Output	Low
EBI_NWR[1:0]	Write Signals	Output	Low
EBI_NRD	Read Signal	Output	Low
EBI_NWE	Write Enable	Output	Low
EBI_NBS[1:0]	Byte Mask Signals	Output	Low
EBI for NAND Flash Support
EBI_NANDCS	NAND Flash Chip Select Line	Output	Low
EBI_NANDOE	NAND Flash Output Enable	Output	Low
EBI_NANDWE	NAND Flash Write Enable	Output	Low
MPDDR Controllers
EBI_SDCK, EBI_SDCK#	MPDDR Differential Clock	Output	–
EBI_SDCK	MPDDR Clock	Output	–
EBI_SDCKE	MPDDR Clock Enable	Output	High
EBI_DDRCS	MPDDR Chip Select Line	Output	Low
EBI_BA[2:0]	Bank Select	Output	–
EBI_SDWE	MPDDR Write Enable	Output	Low
EBI_RAS-EBI_CAS	Row and Column Signal	Output	Low
EBI_SDA10	SDRAM Address 10 Line	Output	–

The connection of some signals through the MUX logic is not direct and depends on the memory controller currently in use.

The following table details the connections between the two memory controllers and the EBI pins.