PLL Locking Mode and Analog Initialization

The PLL is fed by the main crystal oscillator.

The D-PHY consists of 4 data lanes, but applications can use 4 or fewer data lanes. The number of lanes is configured in the field N_LANES in the D-PHY Interface Configuration register (DSI_DPHY_IF_CFG). Configuration of this field must be done prior to exiting Shutdown mode.

Prior to starting normal operation, the following D-PHY parameters must be configured:

• frequency range (refer to High-Speed Frequency Range Control Operation)
• PLL parameters (refer to D-PHY PLL Control Operation).

The initialization period is a protocol-dependent parameter with a minimum of 100 μs defined by the specification.

The D-PHY starts decoding the low-power commands after the analog initialization.