5.5.6.5.5 Clock Lane in Low-Power Mode

To reduce the power consumption of the D-PHY, the DSI host, when not transmitting in High-Speed mode, allows the clock lane to enter Low-Power mode. The controller automatically handles the transition of the clock lane from High-Speed mode (Clock lane active sending clock) to Low-Power mode without direct intervention by the software. This feature can be enabled by configuring the bits PHY_TXREQUESTCLKHS and AUTO_CLKLANE_CTRL in the Clock Lane Control register (DSI_LPCLK_CTRL).

In Command mode, the DSI host can place the clock lane in Low-Power mode when it does not have any High-speed packets to transmit. In Video mode, the Low-Power mode controller uses its internal video and D-PHY timing configurations to determine if there is time available for the clock line to enter Low-Power mode and not compromise the video data transmission of pixel data and sync events.

Along with a correct configuration of Video mode, the DSI host needs to know the time required by the clock and data lanes to go from high-speed to low-power and from low-power to high-speed. The values required can be obtained from the following table. Program the Clock Lane Switch Mode Timing Configuration register (DSI_DPHY_TMR_LPCLK_CFG) and the Data Lane Switch Mode Timing Configuration register (DSI_DPHY_TMR_CFG) with the following values expressed in lane byte clock periods:

Table 5-109. High-Speed Transition Times (expressed in lane byte clock periods)
Frequency Range (MHz)	LP->HS Clock Lane	HS->LP Clock Lane	LP->HS Data Lane	HS->LP Data Lane
80-89	32	20	26	13
90-99	35	23	28	14
100-109	32	22	26	13
110-129	31	20	27	13
130-139	33	22	26	14
140-149	33	21	26	14
150-169	32	20	27	13
170-179	36	23	30	15
180-199	40	22	33	15
200-219	40	22	33	15
220-239	44	24	36	16
240-249	48	24	38	17
250-269	48	24	38	17
270-299	50	27	41	18
300-329	56	28	45	18
330-359	59	28	48	19
360-399	61	30	50	20
400-449	67	31	55	21
450-499	73	31	59	22
500-549	79	36	63	24
550-599	83	37	68	25
600-649	90	38	73	27
650-699	95	40	77	28
700-749	102	40	84	28
750-799	106	42	87	30
800-849	113	44	93	31
850-899	118	47	98	32
900-949	124	47	102	34
950-999	130	49	107	35

Based on the programmed values, the DSI host calculates if there is enough time for the clock lane to enter Low-Power mode during inactive regions of the video frame. There is an exception where the clock lane is activated even when there is no high-speed packet required to be transmitted. If a command is not allowed to be transmitted in any of the available blanking periods, it is transmitted during the last line of the frame.

The DSI host determines the best approach regarding power saving from among the following three possible cases:

There is not sufficient time to enter Low-Power mode. Therefore, a blanking period is added.
Figure 5-50. Clock Lane and Data Lanes in High-Speed mode (HS)
There is sufficient time for the data lanes to enter Low-Power mode but not enough time for the clock lane to enter Low-Power mode.
Figure 5-51. Clock Lane in High-Speed (HS) and Data Lanes in Low-Power Mode (LP)
There is sufficient time for both data lanes and the clock lane to enter Low-Power mode.
Figure 5-52. Clock Lane and Data Lanes in Low-Power Mode (LP)