8.8.6.1 PWM Clock Generator

Figure 8-236. Functional View of the Clock Generator

CAUTION: Before using the PWM controller, the programmer must first enable the PWM clock in the Power Management Controller (PMC).

The PWM peripheral clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. 

The clock generator is divided in three blocks:

a modulo n counter which provides 11 clocks: f_MCK, f_MCK/2, f_MCK/4, f_MCK/8, f_MCK/16, f_MCK/32, f_MCK/64, f_MCK/128, f_MCK/256, f_MCK/512, f_MCK/1024
two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clkA and clkB

Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in PWM_MR.

After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in PWM_MR are set to 0. This implies that after reset clkA (clkB) are turned off.

At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM peripheral clock is turned off through the Power Management Controller.