5.6.6.1.3 Analog Initialization
The D-PHY comprises 4 data lanes, but some applications may require fewer. The number of lanes is configured in the Lane Configuration register (CSI_N_LANES) and must be done only when the D-PHY is in Shutdown mode.
Before starting normal operation, a D-PHY bit rate code must be configured as
shown in the following table. Follow the steps listed below for configuration:
- Ensure that the D-PHY is in Shutdown mode. See Shutdown Mode.
- Reset the analog configuration by generating a high pulse on CSI_PHY_TEST_CTRL0. PHY_TESTCLR.
- Write a ‘1’ to CSI_PHY_TEST_CTRL0.PHY_TESTCLK.
- Write 0x44 to CSI_PHY_TEST_CTRL1.PHY_TESTDIN and write a ‘1’ to CSI_PHY_TEST_CTRL1.PHY_TESTEN.
- Write a ‘0’ to CSI_PHY_TEST_CTRL0.PHY_TESTCLK to create a falling edge on PHY_TESTCLK.
- Write a ‘0’ to CSI_PHY_TEST_CTRL1.PHY_TESTEN and write the configuration value from the following table to CSI_PHY_TEST_CTRL1.PHY_TESTDIN.
- Write a high pulse to CSI_PHY_TEST_CTRL0.PHY_TESTCLK by writing ‘1’ immediately followed by ‘0’.
Range (Mbps) | High-Speed Bit Rate Code |
---|---|
80-89 | 000000 |
90-99 | 010000 |
100-109 | 100000 |
110-129 | 000001 |
130-139 | 010001 |
140-149 | 100001 |
150-169 | 000010 |
170-179 | 010010 |
180-199 | 100010 |
200-219 | 000011 |
220-239 | 010011 |
240-249 | 100011 |
250-269 | 000100 |
270-299 | 010100 |
300-329 | 000101 |
330-359 | 010101 |
360-399 | 100101 |
400-449 | 000110 |
450-499 | 010110 |
500-549 | 000111 |
550-599 | 010111 |
600-649 | 001000 |
650-699 | 011000 |
700-749 | 001001 |
750-799 | 011001 |
800-849 | 101001 |
850-899 | 111001 |
900-949 | 001010 |
950-1000 | 011010 |
The initialization period is a protocol-dependent parameter with a minimum of 100 µs defined by the specification. The D-PHY starts decoding the low-power commands after the analog initialization.