5.6.6.1.3 Analog Initialization

The D-PHY comprises 4 data lanes, but some applications may require fewer. The number of lanes is configured in the Lane Configuration register (CSI_N_LANES) and must be done only when the D-PHY is in Shutdown mode.

Before starting normal operation, a D-PHY bit rate code must be configured as shown in the following table. Follow the steps listed below for configuration:
  1. Ensure that the D-PHY is in Shutdown mode. See Shutdown Mode.
  2. Reset the analog configuration by generating a high pulse on CSI_PHY_TEST_CTRL0. PHY_TESTCLR.
  3. Write a ‘1’ to CSI_PHY_TEST_CTRL0.PHY_TESTCLK.
  4. Write 0x44 to CSI_PHY_TEST_CTRL1.PHY_TESTDIN and write a ‘1’ to CSI_PHY_TEST_CTRL1.PHY_TESTEN.
  5. Write a ‘0’ to CSI_PHY_TEST_CTRL0.PHY_TESTCLK to create a falling edge on PHY_TESTCLK.
  6. Write a ‘0’ to CSI_PHY_TEST_CTRL1.PHY_TESTEN and write the configuration value from the following table to CSI_PHY_TEST_CTRL1.PHY_TESTDIN.
  7. Write a high pulse to CSI_PHY_TEST_CTRL0.PHY_TESTCLK by writing ‘1’ immediately followed by ‘0’.
Table 5-112. Bit Rate Ranges
Range (Mbps)High-Speed Bit Rate Code
80-89000000
90-99010000
100-109100000
110-129000001
130-139010001
140-149100001
150-169000010
170-179010010
180-199100010
200-219000011
220-239010011
240-249100011
250-269000100
270-299010100
300-329000101
330-359010101
360-399100101
400-449000110
450-499010110
500-549000111
550-599010111
600-649001000
650-699011000
700-749001001
750-799011001
800-849101001
850-899111001
900-949001010
950-1000011010

The initialization period is a protocol-dependent parameter with a minimum of 100 µs defined by the specification. The D-PHY starts decoding the low-power commands after the analog initialization.