3.3.15 Asynchronous Page Mode

The SMC supports asynchronous burst reads in Page mode, providing that the Page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.

The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in the table below.

With Page mode memory devices, the first access to one page (t_pa) takes longer than the subsequent accesses to the page (t_sa) as shown in Figure 3-43. When in Page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page.

Table 3-10. Page Address and Data Address Within a Page
Page Size	Page Address ⁽¹⁾	Data Address in the Page ⁽²⁾
4 bytes	A[22:2]	A[1:0]
8 bytes	A[22:3]	A[2:0]
16 bytes	A[22:4]	A[3:0]
32 bytes	A[22:5]	A[4:0]

Note:

‘A’ denotes the address bus of the memory device.
For 16-bit devices, bit 0 of the address is ignored.