5.3.6.1 Introduction

The LVDSC is driven by the LCD Controller and drives the LVDS physical interface (LVDS PHY). The LVDSC embeds the bit mapping circuitry and configures the serializers located in the LVDS PHY.

The LCDC peripheral clock and pixel clock must be enabled to configure the LVDSC.

The operating modes of the LVDSC are configured in the Configuration register (LVDSC_CFGR). The configuration status bit CS in the Status register (LVDSC_SR) must be read at 0 prior to writing a new value in LVDSC_CFGR and in the User Control Bits register (LVDSC_UCBR).

When the configuration is complete, the LVDSC must be enabled by writing a ‘1’ to the bit SER_EN in the Control register (LVDSC_CR).

LVDSC_CFGR and LVDSC_UCBR cannot be modified when LVDSC_CR.SER_EN=1.

The reserved bit of the LVDS frame can be configured in LVDSC_UCBR.