2.4.4 DMA Controller Peripheral Connections

DMA Controller 0 manages transfers between peripherals and memory, and receives the triggers from the peripherals listed in the following table.

Table 2-10. DMA Channels Definitions (XDMAC0)
Instance NameChannel T/RInterface Number
FLEXCOM0Transmit0
FLEXCOM0Receive1
FLEXCOM1Transmit2
FLEXCOM1Receive3
FLEXCOM2Transmit4
FLEXCOM2Receive5
FLEXCOM3Transmit6
FLEXCOM3Receive7
FLEXCOM4Transmit8
FLEXCOM4Receive9
FLEXCOM5Transmit10
FLEXCOM5Receive11
FLEXCOM6Transmit12
FLEXCOM6Receive13
FLEXCOM7Transmit14
FLEXCOM7Receive15
FLEXCOM8Transmit16
FLEXCOM8Receive17
FLEXCOM9Transmit18
FLEXCOM9Receive19
FLEXCOM10Transmit20
FLEXCOM10Receive21
FLEXCOM11Transmit22
FLEXCOM11Receive23
FLEXCOM12Transmit24
FLEXCOM12Receive25
QSPITransmit26
QSPIReceive27
DBGUTransmit28
DBGUReceive29
TDESReceive30
TDESTransmit31
AESTransmit32
AESReceive33
SHATransmit34
CLASSDTransmit35
I2SMCCTransmit36
I2SMCCReceive37
SSCTransmit38
SSCReceive39
ADCReceive40
TC0Receive41
TC1Receive42
TC1_CPACompare Counter A, Timer Channel 143
TC4_CPACompare Counter A, Timer Channel 444
TC1_CPBCompare Counter B, Timer Channel 145
TC4_CPBCompare Counter B Timer Channel 446
TC1_CPCCompare Counter C, Timer Channel 147
TC4_CPCCompare Counter C, Timer Channel 448
TC1_ETRGExternal Event trigger, timer channel 1 for TC1_ETRG49
TC4_ETRGExternal Event trigger, timer channel 1 for TC4_ETRG50