4.11.4 Functional Description

The Periodic Interval Timer (PIT) provides periodic interrupts for use by operating systems.

The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Main System Bus Clock /16.

The 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments PICNT. The status bit PITS in the Status register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PIT_MR.PITIEN).

Writing a new PIV value in PIT_MR does not reset/restart the counters.

When CPIV and PICNT values are obtained by reading the Periodic Interval Value register (PIT_PIVR), the overflow counter (PICNT) is reset and PIT_SR.PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR.

When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.

The PIT may be enabled/disabled using PIT_MR.PITEN (disabled on reset). PITEN only becomes effective when the CPIV value is 0. The figure below illustrates the PIT counting. After PITEN is reset (PITEN = 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if PITEN is set again.

The PIT is stopped when the core enters debug state.