Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
128-bit/192-bit/256-bit Cryptographic Key
10/12/14 Clock Cycles Encryption/Decryption Inherent Processing
Time with a 128-bit/192-bit/256-bit Cryptographic Key
Double Input Buffer Optimizes Runtime
Automatic Padding
supported for IPSec and SSL standards
IPSec and SSL Protocol
Layers Improved Performances (Tightly coupled with SHA)
Support of the Modes of Operation Specified in the NIST Special
Publication 800-38A and NIST Special Publication
800-38D and NIST Special Publication
800-38E:
Electronic Codebook (ECB)
Cipher Block Chaining (CBC) including CBC-MAC
Cipher Feedback (CFB)
Output Feedback (OFB)
Counter (CTR)
Galois/Counter Mode
(GCM)
XEX-Based
Tweaked-Codebook Mode (XTS)
8, 16, 32, 64 and 128-bit Data Sizes Possible in CFB Mode
Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation
Abnormal Software
Access and Internal Sequencer Integrity Check Reports
Register Write Protection
Temporary Secure Storage for Keys
Private Key Bus
Access to the Private Key Internal Register Not Readable from any Peripheral or
Software
Connection to DMA Optimizes Data Transfers for all Operating Modes
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
