8.3.8.8.2 Two-Pin Mode Configuration

The Two-Pin mode is enabled when FLEX_SPI_MR.TPMEN=1 and FLEX_SPI_MR.MSTR=0.

When Two-Pin mode is enabled, SPI Mode 0 must be configured (FLEX_SPI_CSR0.CPOL=0 and FLEX_SPI_CSR0.NCPHA=0) and the data length must be 8 bits (FLEX_SPI_CSRx.BITS=0).

For proper CRC calculation and checking, FLEX_SPI_CRCR.FHE must be set to '0', FLEX_SPI_CRCR.CRM to '0', FLEX_SPI_CRCR.FRHL to '1' and FLEX_SPI_CRCR.CRCS to '0'. MCSPI_CRCR.FRL must be set according to the value used for FLEX_SPI_TPMR.OSR (refer to “Two-Wire Serial Interface Description” in the data sheet “MCP3910” available on www.microchip.com for more details on frame length and OSR).

See SPI CRC Generation and Checking for details on CRC check configuration.

To get the synchronization on SYNC BYTE, the Comparison mode must be enabled (FLEX_SPI_MR.CMPMODE=1) and the comparison value must be configured to SYNC BYTE (FLEX_SPI_CMPR.VAL1/2= 0xA5). The clock is generated on SPCK when FLEX_SPI_CR.SPIEN is set.

Once the SPI is configured in Two-Pin mode and Comparison mode is set, the synchronization byte (SYNC BYTE) is monitored to start receiving a frame. Upon SYNC BYTE reception, the previously received header byte is stored in the Two-Pin Header register (FLEX_SPI_TPHR) and the SYNC BYTE is stored in FLEX_SPI_RDR (the RDRF flag indicates when the data is available). Each frame byte received is written in FLEX_SPI_RDR until reception of the CRCCOM end field (CRC is received as a data).

The Oversampling Rate (OSR) field in the Two-Pin Mode register (FLEX_SPI_TPMR) defines the OSR frame configuration of the MCP3910, and thus the frame length.