2.5.1.4.10 QSPI NOR Flash Boot

Hardware Considerations

The ROM code configures the hardware so that:

  • the QSPI controller uses SPI Mode 0 (CPOL = 0 and CPHA = 0),
  • the QSPIx_SCK clock frequency is ≤ 50 MHz,
  • QSPIx_SCK and QSPIx_CS do not use any internal pull-up/pull-down resistor,
  • each QSPIx_IO{0,1,2,3} uses the PIO controller’s internal pull-up resistor.

Software Considerations

Before reading any data, the ROM code sends a software reset to the QSPI NOR memory. Then the ROM code looks for the Serial Flash Discoverable Parameters (SFDP) of the QSPI NOR memory, if available, to learn the parameters (instruction op code, timing settings) required to read the user-programmed boot file.

If SFDP tables are not available, the ROM code uses hard-coded values as fallback settings to read the boot file.

The ROM code supports any QSPI NOR memory which can provide its Serial Flash Discoverable Parameters (SFDP) as defined in the JEDEC® JESD216B standard.

The supported revisions of this JEDEC standard are:

  • JESD216 (version 1.0)
  • JESD216 rev. A (version 1.5)
  • JESD216 rev. B (version 1.6)

Refer to the QSPI NOR memory data sheet to check compliance with any of the above JEDEC JESD216 standard revisions/versions.

QSPI NOR Memories with SFDP (JEDEC JESD216x Compliant)

The ROM code reads the memory SFDP tables to learn the factory settings (instruction op code, number of dummy cycles, etc.). The ROM code also reads bits[22:20] in DWORD15 from the Basic Flash Parameter table (refer to the JEDEC JESD216B specification) to select and then execute the relevant procedure, if any, to set the Quad Enable (QE) bit in some internal register of the QSPI NOR memory.

For most memory manufacturers, this QE bit is non-volatile and must be set before performing any Quad SPI command. This is the only persistent setting that the ROM code may change in the internal registers of the QSPI NOR memory. All other settings are kept unchanged.

Refer to the QSPI NOR memory data sheet to find which value was chosen by the memory manufacturer and written into the SFDP tables.

Finally, the ROM code reads the boot file from the data area of the QSPI NOR memory, and then continues its boot procedure.

QSPI NOR Memories without SFDP

This section only applies when the ROM code fails to read the SFDP tables from the QSPI NOR memory.

The ROM code reads the JEDEC ID of the QSPI NOR memory, and then selects the read settings based on the manufacturer ID (first byte of the JEDEC ID) from the following hard-coded values:

Table 2-14. QSPI NOR Memories Settings
Cypress (01h)Micron (20h)Macronix (C2h)Winbond (EFh)Others
Fast Read protocolSPI 1-4-4SPI 1-4-4SPI 1-4-4SPI 1-4-4SPI 1-1-1
Fast Read op codeEBhEBhEBhEBh0Bh
Address width24 bits24 bits24 bits24 bits24 bits
Number of mode clock cycles21220
Number of wait states49448
Value of mode cycles to enter the 0-4-4 mode (XIP)A0h0h

The ROM code first sets SIP bit[3] in the Volatile Configuration register (VCR)

0FhA5hN/A
Value of mode cycles to exit the 0-4-4 mode (normal read)00h1h00hFFhN/A
XIP supportedYesYesYesYesNo

Those hard-coded parameters give a last chance to the ROM code to boot from a QSPI NOR memory in either Normal mode or XIP (Continuous Read) mode.

Table 2-15. QSPI NOR Memories Tested with and Supported by ROM Code (Non Exhaustive)
ManufacturerMemories
Microchip (SST)SST26VF016B

SST26VF032B

SST26VF032BA

SST26VF064B

MicronN25Q128A

N25Q128A13ESF

N25Q256A13ESF

N25Q512A13

MT25QL01G

MacronixMX25V4035FM2I

MX25V8035FM2I

MX25V1635FM2I

MX25L3233FM2I-08G

MX25L3273FM2I-08G

MX25L6433FM2I-08G

MX25L6473FM2I-08G

MX25L12835FM2I-10G

MX25L12845GMI-08G

MX25L12873GM2I-08G

MX25L25645G

MX25L25673G

MX25L51245GMI-10G

MX66L1G45GMI-08G

SpansionS25FL127 (normal boot only; XIP fails)

S25FL164

S25FL512

WinbondW25M512
Note: For an updated list of memories, refer to the “Booting from External Non-Volatile Memory (NVM) on SAM9X7 Series MPUs” (AN4971) application note, available on www.microchip.com.