10.2 Register Summary

Note: The registers below have two modes: Control, Bulk, Interrupt Endpoints mode and Isochronous Endpoints mode. In this register summary, both modes are displayed at the same offset.

UDPHS_EPTCTLENB
UDPHS_EPTCTLDIS
UDPHS_EPTCTL
UDPHS_EPTSETSTA
UDPHS_EPTCLRSTA
UDPHS_EPTSTA


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	UDPHS_CTRL	31:24
		23:16
		15:8					PULLD_DIS	REWAKEUP	DETACH	EN_UDPHS
		7:0	FADDR_EN	DEV_ADDR[6:0]
0x04	UDPHS_FNUM	31:24	FNUM_ERR
		23:16
		15:8			FRAME_NUMBER[10:5]
		7:0	FRAME_NUMBER[4:0]					MICRO_FRAME_NUM[2:0]
0x08 ... 0x0F	Reserved
0x10	UDPHS_IEN	31:24		DMA_6	DMA_5	DMA_4	DMA_3	DMA_2	DMA_1
		23:16
		15:8		EPT_6	EPT_5	EPT_4	EPT_3	EPT_2	EPT_1	EPT_0
		7:0	UPSTR_RES	ENDOFRSM	WAKE_UP	ENDRESET	INT_SOF	MICRO_SOF	DET_SUSPD
0x14	UDPHS_INTSTA	31:24		DMA_6	DMA_5	DMA_4	DMA_3	DMA_2	DMA_1
		23:16
		15:8		EPT_6	EPT_5	EPT_4	EPT_3	EPT_2	EPT_1	EPT_0
		7:0	UPSTR_RES	ENDOFRSM	WAKE_UP	ENDRESET	INT_SOF	MICRO_SOF	DET_SUSPD	SPEED
0x18	UDPHS_CLRINT	31:24
		23:16
		15:8
		7:0	UPSTR_RES	ENDOFRSM	WAKE_UP	ENDRESET	INT_SOF	MICRO_SOF	DET_SUSPD
0x1C	UDPHS_EPTRST	31:24
		23:16
		15:8
		7:0		EPT_6	EPT_5	EPT_4	EPT_3	EPT_2	EPT_1	EPT_0
0x20 ... 0xDF	Reserved
0xE0	UDPHS_TST	31:24
		23:16
		15:8
		7:0			OPMODE2	TST_PKT	TST_K	TST_J	SPEED_CFG[1:0]
0xE4 ... 0xFF	Reserved
0x0100	UDPHS_EPTCFG0	31:24	EPT_MAPD
		23:16
		15:8							NB_TRANS[1:0]
		7:0	BK_NUMBER[1:0]		EPT_TYPE[1:0]		EPT_DIR	EPT_SIZE[2:0]
0x0104	UDPHS_EPTCTLENB0 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0104	UDPHS_EPTCTLENB0 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0108	UDPHS_EPTCTLDIS0 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x0108	UDPHS_EPTCTLDIS0 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x010C	UDPHS_EPTCTL0 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x010C	UDPHS_EPTCTL0 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0110 ... 0x0113	Reserved
0x0114	UDPHS_EPTSETSTA0 (DEFAULT_MODE)	31:24
		23:16
		15:8					TXRDY		RXRDY_TXKL
		7:0			FRCESTALL
0x0114	UDPHS_EPTSETSTA0 (ISOENDPT)	31:24
		23:16
		15:8					TXRDY_TRER		RXRDY_TXKL
		7:0
0x0118	UDPHS_EPTCLRSTA0 (DEFAULT_MODE)	31:24
		23:16
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ	FRCESTALL
0x0118	UDPHS_EPTCLRSTA0 (ISOENDPT)	31:24
		23:16
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ
0x011C	UDPHS_EPTSTA0 (DEFAULT_MODE)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK_CTLDIR[1:0]
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]		FRCESTALL
0x011C	UDPHS_EPTSTA0 (ISOENDPT)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK[1:0]
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]
0x0120	UDPHS_EPTCFG1	31:24	EPT_MAPD
		23:16
		15:8							NB_TRANS[1:0]
		7:0	BK_NUMBER[1:0]		EPT_TYPE[1:0]		EPT_DIR	EPT_SIZE[2:0]
0x0124	UDPHS_EPTCTLENB1 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0124	UDPHS_EPTCTLENB1 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0128	UDPHS_EPTCTLDIS1 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x0128	UDPHS_EPTCTLDIS1 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x012C	UDPHS_EPTCTL1 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x012C	UDPHS_EPTCTL1 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0130 ... 0x0133	Reserved
0x0134	UDPHS_EPTSETSTA1 (DEFAULT_MODE)	31:24
		23:16
		15:8					TXRDY		RXRDY_TXKL
		7:0			FRCESTALL
0x0134	UDPHS_EPTSETSTA1 (ISOENDPT)	31:24
		23:16
		15:8					TXRDY_TRER		RXRDY_TXKL
		7:0
0x0138	UDPHS_EPTCLRSTA1 (DEFAULT_MODE)	31:24
		23:16
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ	FRCESTALL
0x0138	UDPHS_EPTCLRSTA1 (ISOENDPT)	31:24
		23:16
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ
0x013C	UDPHS_EPTSTA1 (DEFAULT_MODE)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK_CTLDIR[1:0]
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]		FRCESTALL
0x013C	UDPHS_EPTSTA1 (ISOENDPT)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK[1:0]
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]
0x0140	UDPHS_EPTCFG2	31:24	EPT_MAPD
		23:16
		15:8							NB_TRANS[1:0]
		7:0	BK_NUMBER[1:0]		EPT_TYPE[1:0]		EPT_DIR	EPT_SIZE[2:0]
0x0144	UDPHS_EPTCTLENB2 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0144	UDPHS_EPTCTLENB2 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0148	UDPHS_EPTCTLDIS2 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x0148	UDPHS_EPTCTLDIS2 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x014C	UDPHS_EPTCTL2 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x014C	UDPHS_EPTCTL2 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0150 ... 0x0153	Reserved
0x0154	UDPHS_EPTSETSTA2 (DEFAULT_MODE)	31:24
		23:16
		15:8					TXRDY		RXRDY_TXKL
		7:0			FRCESTALL
0x0154	UDPHS_EPTSETSTA2 (ISOENDPT)	31:24
		23:16
		15:8					TXRDY_TRER		RXRDY_TXKL
		7:0
0x0158	UDPHS_EPTCLRSTA2 (DEFAULT_MODE)	31:24
		23:16
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ	FRCESTALL
0x0158	UDPHS_EPTCLRSTA2 (ISOENDPT)	31:24
		23:16
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ
0x015C	UDPHS_EPTSTA2 (DEFAULT_MODE)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK_CTLDIR[1:0]
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]		FRCESTALL
0x015C	UDPHS_EPTSTA2 (ISOENDPT)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK[1:0]
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]
0x0160	UDPHS_EPTCFG3	31:24	EPT_MAPD
		23:16
		15:8							NB_TRANS[1:0]
		7:0	BK_NUMBER[1:0]		EPT_TYPE[1:0]		EPT_DIR	EPT_SIZE[2:0]
0x0164	UDPHS_EPTCTLENB3 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0164	UDPHS_EPTCTLENB3 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0168	UDPHS_EPTCTLDIS3 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x0168	UDPHS_EPTCTLDIS3 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x016C	UDPHS_EPTCTL3 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x016C	UDPHS_EPTCTL3 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0170 ... 0x0173	Reserved
0x0174	UDPHS_EPTSETSTA3 (DEFAULT_MODE)	31:24
		23:16
		15:8					TXRDY		RXRDY_TXKL
		7:0			FRCESTALL
0x0174	UDPHS_EPTSETSTA3 (ISOENDPT)	31:24
		23:16
		15:8					TXRDY_TRER		RXRDY_TXKL
		7:0
0x0178	UDPHS_EPTCLRSTA3 (DEFAULT_MODE)	31:24
		23:16
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ	FRCESTALL
0x0178	UDPHS_EPTCLRSTA3 (ISOENDPT)	31:24
		23:16
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ
0x017C	UDPHS_EPTSTA3 (DEFAULT_MODE)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK_CTLDIR[1:0]
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]		FRCESTALL
0x017C	UDPHS_EPTSTA3 (ISOENDPT)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK[1:0]
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]
0x0180	UDPHS_EPTCFG4	31:24	EPT_MAPD
		23:16
		15:8							NB_TRANS[1:0]
		7:0	BK_NUMBER[1:0]		EPT_TYPE[1:0]		EPT_DIR	EPT_SIZE[2:0]
0x0184	UDPHS_EPTCTLENB4 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0184	UDPHS_EPTCTLENB4 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0188	UDPHS_EPTCTLDIS4 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x0188	UDPHS_EPTCTLDIS4 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x018C	UDPHS_EPTCTL4 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x018C	UDPHS_EPTCTL4 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x0190 ... 0x0193	Reserved
0x0194	UDPHS_EPTSETSTA4 (DEFAULT_MODE)	31:24
		23:16
		15:8					TXRDY		RXRDY_TXKL
		7:0			FRCESTALL
0x0194	UDPHS_EPTSETSTA4 (ISOENDPT)	31:24
		23:16
		15:8					TXRDY_TRER		RXRDY_TXKL
		7:0
0x0198	UDPHS_EPTCLRSTA4 (DEFAULT_MODE)	31:24
		23:16
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ	FRCESTALL
0x0198	UDPHS_EPTCLRSTA4 (ISOENDPT)	31:24
		23:16
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ
0x019C	UDPHS_EPTSTA4 (DEFAULT_MODE)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK_CTLDIR[1:0]
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]		FRCESTALL
0x019C	UDPHS_EPTSTA4 (ISOENDPT)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK[1:0]
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]
0x01A0	UDPHS_EPTCFG5	31:24	EPT_MAPD
		23:16
		15:8							NB_TRANS[1:0]
		7:0	BK_NUMBER[1:0]		EPT_TYPE[1:0]		EPT_DIR	EPT_SIZE[2:0]
0x01A4	UDPHS_EPTCTLENB5 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01A4	UDPHS_EPTCTLENB5 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01A8	UDPHS_EPTCTLDIS5 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x01A8	UDPHS_EPTCTLDIS5 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x01AC	UDPHS_EPTCTL5 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01AC	UDPHS_EPTCTL5 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01B0 ... 0x01B3	Reserved
0x01B4	UDPHS_EPTSETSTA5 (DEFAULT_MODE)	31:24
		23:16
		15:8					TXRDY		RXRDY_TXKL
		7:0			FRCESTALL
0x01B4	UDPHS_EPTSETSTA5 (ISOENDPT)	31:24
		23:16
		15:8					TXRDY_TRER		RXRDY_TXKL
		7:0
0x01B8	UDPHS_EPTCLRSTA5 (DEFAULT_MODE)	31:24
		23:16
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ	FRCESTALL
0x01B8	UDPHS_EPTCLRSTA5 (ISOENDPT)	31:24
		23:16
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ
0x01BC	UDPHS_EPTSTA5 (DEFAULT_MODE)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK_CTLDIR[1:0]
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]		FRCESTALL
0x01BC	UDPHS_EPTSTA5 (ISOENDPT)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK[1:0]
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]
0x01C0	UDPHS_EPTCFG6	31:24	EPT_MAPD
		23:16
		15:8							NB_TRANS[1:0]
		7:0	BK_NUMBER[1:0]		EPT_TYPE[1:0]		EPT_DIR	EPT_SIZE[2:0]
0x01C4	UDPHS_EPTCTLENB6 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01C4	UDPHS_EPTCTLENB6 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01C8	UDPHS_EPTCTLDIS6 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x01C8	UDPHS_EPTCTLDIS6 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_DISABL
0x01CC	UDPHS_EPTCTL6 (DEFAULT_MODE)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0				NYET_DIS	INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01CC	UDPHS_EPTCTL6 (ISOENDPT)	31:24	SHRT_PCKT
		23:16						BUSY_BANK
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	MDATA_RX	DATAX_RX			INTDIS_DMA		AUTO_VALID	EPT_ENABL
0x01D0 ... 0x01D3	Reserved
0x01D4	UDPHS_EPTSETSTA6 (DEFAULT_MODE)	31:24
		23:16
		15:8					TXRDY		RXRDY_TXKL
		7:0			FRCESTALL
0x01D4	UDPHS_EPTSETSTA6 (ISOENDPT)	31:24
		23:16
		15:8					TXRDY_TRER		RXRDY_TXKL
		7:0
0x01D8	UDPHS_EPTCLRSTA6 (DEFAULT_MODE)	31:24
		23:16
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ	FRCESTALL
0x01D8	UDPHS_EPTCLRSTA6 (ISOENDPT)	31:24
		23:16
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO		TX_COMPLT	RXRDY_TXKL
		7:0		TOGGLESQ
0x01DC	UDPHS_EPTSTA6 (DEFAULT_MODE)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK_CTLDIR[1:0]
		15:8	NAK_OUT	NAK_IN	STALL_SNT	RX_SETUP	TXRDY	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]		FRCESTALL
0x01DC	UDPHS_EPTSTA6 (ISOENDPT)	31:24	SHRT_PCKT	BYTE_COUNT[10:4]
		23:16	BYTE_COUNT[3:0]				BUSY_BANK_STA[1:0]		CURBK[1:0]
		15:8		ERR_FLUSH	ERR_CRC_NTR	ERR_FL_ISO	TXRDY_TRER	TX_COMPLT	RXRDY_TXKL	ERR_OVFLW
		7:0	TOGGLESQ_STA[1:0]
0x01E0 ... 0x030F	Reserved
0x0310	UDPHS_DMANXTDSC1	31:24	NXT_DSC_ADD[31:24]
		23:16	NXT_DSC_ADD[23:16]
		15:8	NXT_DSC_ADD[15:8]
		7:0	NXT_DSC_ADD[7:0]
0x0314	UDPHS_DMAADDRESS1	31:24	BUFF_ADD[31:24]
		23:16	BUFF_ADD[23:16]
		15:8	BUFF_ADD[15:8]
		7:0	BUFF_ADD[7:0]
0x0318	UDPHS_DMACONTROL1	31:24	BUFF_LENGTH[15:8]
		23:16	BUFF_LENGTH[7:0]
		15:8
		7:0	BURST_LCK	DESC_LD_IT	END_BUFFIT	END_TR_IT	END_B_EN	END_TR_EN	LDNXT_DSC	CHANN_ENB
0x031C	UDPHS_DMASTATUS1	31:24	BUFF_COUNT[15:8]
		23:16	BUFF_COUNT[7:0]
		15:8
		7:0		DESC_LDST	END_BF_ST	END_TR_ST			CHANN_ACT	CHANN_ENB
0x0320	UDPHS_DMANXTDSC2	31:24	NXT_DSC_ADD[31:24]
		23:16	NXT_DSC_ADD[23:16]
		15:8	NXT_DSC_ADD[15:8]
		7:0	NXT_DSC_ADD[7:0]
0x0324	UDPHS_DMAADDRESS2	31:24	BUFF_ADD[31:24]
		23:16	BUFF_ADD[23:16]
		15:8	BUFF_ADD[15:8]
		7:0	BUFF_ADD[7:0]
0x0328	UDPHS_DMACONTROL2	31:24	BUFF_LENGTH[15:8]
		23:16	BUFF_LENGTH[7:0]
		15:8
		7:0	BURST_LCK	DESC_LD_IT	END_BUFFIT	END_TR_IT	END_B_EN	END_TR_EN	LDNXT_DSC	CHANN_ENB
0x032C	UDPHS_DMASTATUS2	31:24	BUFF_COUNT[15:8]
		23:16	BUFF_COUNT[7:0]
		15:8
		7:0		DESC_LDST	END_BF_ST	END_TR_ST			CHANN_ACT	CHANN_ENB
0x0330	UDPHS_DMANXTDSC3	31:24	NXT_DSC_ADD[31:24]
		23:16	NXT_DSC_ADD[23:16]
		15:8	NXT_DSC_ADD[15:8]
		7:0	NXT_DSC_ADD[7:0]
0x0334	UDPHS_DMAADDRESS3	31:24	BUFF_ADD[31:24]
		23:16	BUFF_ADD[23:16]
		15:8	BUFF_ADD[15:8]
		7:0	BUFF_ADD[7:0]
0x0338	UDPHS_DMACONTROL3	31:24	BUFF_LENGTH[15:8]
		23:16	BUFF_LENGTH[7:0]
		15:8
		7:0	BURST_LCK	DESC_LD_IT	END_BUFFIT	END_TR_IT	END_B_EN	END_TR_EN	LDNXT_DSC	CHANN_ENB
0x033C	UDPHS_DMASTATUS3	31:24	BUFF_COUNT[15:8]
		23:16	BUFF_COUNT[7:0]
		15:8
		7:0		DESC_LDST	END_BF_ST	END_TR_ST			CHANN_ACT	CHANN_ENB
0x0340	UDPHS_DMANXTDSC4	31:24	NXT_DSC_ADD[31:24]
		23:16	NXT_DSC_ADD[23:16]
		15:8	NXT_DSC_ADD[15:8]
		7:0	NXT_DSC_ADD[7:0]
0x0344	UDPHS_DMAADDRESS4	31:24	BUFF_ADD[31:24]
		23:16	BUFF_ADD[23:16]
		15:8	BUFF_ADD[15:8]
		7:0	BUFF_ADD[7:0]
0x0348	UDPHS_DMACONTROL4	31:24	BUFF_LENGTH[15:8]
		23:16	BUFF_LENGTH[7:0]
		15:8
		7:0	BURST_LCK	DESC_LD_IT	END_BUFFIT	END_TR_IT	END_B_EN	END_TR_EN	LDNXT_DSC	CHANN_ENB
0x034C	UDPHS_DMASTATUS4	31:24	BUFF_COUNT[15:8]
		23:16	BUFF_COUNT[7:0]
		15:8
		7:0		DESC_LDST	END_BF_ST	END_TR_ST			CHANN_ACT	CHANN_ENB
0x0350	UDPHS_DMANXTDSC5	31:24	NXT_DSC_ADD[31:24]
		23:16	NXT_DSC_ADD[23:16]
		15:8	NXT_DSC_ADD[15:8]
		7:0	NXT_DSC_ADD[7:0]
0x0354	UDPHS_DMAADDRESS5	31:24	BUFF_ADD[31:24]
		23:16	BUFF_ADD[23:16]
		15:8	BUFF_ADD[15:8]
		7:0	BUFF_ADD[7:0]
0x0358	UDPHS_DMACONTROL5	31:24	BUFF_LENGTH[15:8]
		23:16	BUFF_LENGTH[7:0]
		15:8
		7:0	BURST_LCK	DESC_LD_IT	END_BUFFIT	END_TR_IT	END_B_EN	END_TR_EN	LDNXT_DSC	CHANN_ENB
0x035C	UDPHS_DMASTATUS5	31:24	BUFF_COUNT[15:8]
		23:16	BUFF_COUNT[7:0]
		15:8
		7:0		DESC_LDST	END_BF_ST	END_TR_ST			CHANN_ACT	CHANN_ENB
0x0360	UDPHS_DMANXTDSC6	31:24	NXT_DSC_ADD[31:24]
		23:16	NXT_DSC_ADD[23:16]
		15:8	NXT_DSC_ADD[15:8]
		7:0	NXT_DSC_ADD[7:0]
0x0364	UDPHS_DMAADDRESS6	31:24	BUFF_ADD[31:24]
		23:16	BUFF_ADD[23:16]
		15:8	BUFF_ADD[15:8]
		7:0	BUFF_ADD[7:0]
0x0368	UDPHS_DMACONTROL6	31:24	BUFF_LENGTH[15:8]
		23:16	BUFF_LENGTH[7:0]
		15:8
		7:0	BURST_LCK	DESC_LD_IT	END_BUFFIT	END_TR_IT	END_B_EN	END_TR_EN	LDNXT_DSC	CHANN_ENB
0x036C	UDPHS_DMASTATUS6	31:24	BUFF_COUNT[15:8]
		23:16	BUFF_COUNT[7:0]
		15:8
		7:0		DESC_LDST	END_BF_ST	END_TR_ST			CHANN_ACT	CHANN_ENB