2.5.4 Hardware Considerations

The table below provides clock frequencies configured by the ROM code during boot.

Table 2-25. Clock Frequencies During External Memory Boot Sequence
ClockFrequency
PLLA1200 MHz
CPU_CLK600 MHz
MCK200 MHz
SDMMC (init/operational)400 kHz/25 MHz
QSPI50 MHz

The default UART used for ROM code console and SAM-BA Monitor UART link is given below:

Index Value in CONSOLE_IOSET[5:0] BitInterface
0DBGU

The default can be changed by writing another index in the Boot Configuration Packet (refer to CONSOLE_PIN).

The NVM drivers use several PIOs in Peripheral mode to communicate with external Flash memory devices. Care must be taken when these PIOs are used by the application. The connected devices could be unintentionally driven at boot time, and thus electrical conflicts between the output pins used by the NVM drivers and the connected devices could occur.

The following table contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. The drive strength of pull-up I/O pins is set to High while the pins are used in Peripheral mode by the ROM code.

Before performing the jump to the application in the internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state.

Table 2-26. PIO Driven During Boot Program Execution
NVM BootloaderPeripheralIO SetSignalPIO LinePull-up enabled
SD Card/e.MMCSDMMC_01SDMMC0_DAT0PIO_PA0AY
SDMMC0_CMDPIO_PA1AY
SDMMC0_CKPIO_PA2A–
SDMMC0_DAT1PIO_PA3AY
SDMMC0_DAT2PIO_PA4AY
SDMMC0_DAT3PIO_PA5AY
SDMMC_11SDMMC1_DAT0PIO_PA9BY
SDMMC1_DAT1PIO_PA6BY
SDMMC1_DAT2PIO_PA7BY
SDMMC1_DAT3PIO_PA8BY
SDMMC1_CMDPIO_PA10BY
–
SDMMC1_CKPIO_PA11B
NAND FlashHSMC1NANDOEPIO_PD0A–
NANDWEPIO_PD1A–
NANDALEPIO_PD2A–
NANDCLEPIO_PD3A–
NANDCSPIO_PD4A–
NAND WAITPIO_PD14A–
D0-D7PIO_PD6A-PIO_PD13AY
SPI FlashFLEXCOM01MOSIPIO_PA31AY
MISOPIO_PA30A–
NPCS0PIO_PA3A–
SPCKPIO_PA8A–
2MOSIPIO_PA0AY
MISOPIO_PA1A–
NPCS1PIO_PA2A–
SPCKPIO_PA4A–
FLEXCOM11MOSIPIO_PA5AY
MISOPIO_PA6A–
NPCS0PIO_PC28C–
SPCKPIO_PC29C–
2MOSIPIO_PA5AY
MISOPIO_PA6A–
NPCS1PIO_PC27C–
SPCKPIO_PC29C–
FLEXCOM21MOSIPIO_PA7AY
MISOPIO_PA8A–
SPCKPIO_PB1B–
NPCS0PIO_PB2B–
2MOSIPIO_PA7AY
MISOPIO_PA8A–
SPCKPIO_PB2B–
NPCS1PIO_PB0B–
FLEXCOM31MOSIPIO_PC22BY
MISOPIO_PC23B–
NPCS0PIO_PC25B–
SPCKPIO_PC26B–
2MOSIPIO_PC22BY
MISOPIO_PC23B–
NPCS1PIO_PC24B–
SPCKPIO_PC26B–
SPI FlashFLEXCOM41MISOPIO_PA11A–
MOSIPIO_PA12AY
SPCKPIO_PA13A–
NPCS0PIO_PA14A–
2MISOPIO_PA11A–
MOSIPIO_PA12AY
SPCKPIO_PA13A–
NPCS1PIO_PA0C–
3MISOPIO_PA11A–
MOSIPIO_PA12AY
SPCKPIO_PA13A–
NPCS1PIO_PA7B–
4MISOPIO_PA11A–
MOSIPIO_PA12AY
SPCKPIO_PA13A–
NPCS2PIO_PA1B–
5MISOPIO_PA11A–
MOSIPIO_PA12AY
SPCKPIO_PA13A–
NPCS2PIO_PA8C–
6MISOPIO_PA11A–
MOSIPIO_PA12AY
SPCKPIO_PA13A–
NPCS3PIO_PB3B–
SPI FlashFLEXCOM51NPCS0PIO_PA8B–
MISOPIO_PA21B–
MOSIPIO_PA22BY
SPCKPIO_PA23B–
2NPCS1PIO_PA0B–
MISOPIO_PA21B–
MOSIPIO_PA22BY
SPCKPIO_PA23B–
3MISOPIO_PA21B–
MOSIPIO_PA22BY
SPCKPIO_PA23B–
NPCS1PIO_PA7C–
4MISOPIO_PA21B–
MOSIPIO_PA22BY
SPCKPIO_PA23B–
NPCS2PIO_PA31B–
5MISOPIO_PA21B–
MOSIPIO_PA22BY
SPCKPIO_PA23B–
NPCS3PIO_PA30B–
QSPI NOR FlashQSPI01QSCKPIO_PB19A–
QCSPIO_PB20A–
QIO0PIO_PB21AX
QIO1PIO_PB22AX
QIO2PIO_PB23AX
QIO3PIO_PB24AX
ROM code console and SAM-BA MonitorDBGU1DTXDPIO_PA27A–
DRXDPIO_PA26AX
FLEXCOM01DTXDPIO_PA30A–
DRXDPIO_PA31AX
FLEXCOM11DTXDPIO_PA28A–
DRXDPIO_PA29AX
FLEXCOM21DTXDPIO_PA13A–
DRXDPIO_PA14AX
FLEXCOM31DTXDPIO_PC22B–
DRXDPIO_PC23BX
FLEXCOM41DTXDPIO_PA10A–
DRXDPIO_PA9AX
FLEXCOM51DTXDPIO_PA16B–
DRXDPIO_PA15BX
FLEXCOM61DTXDPIO_PA14A–
DRXDPIO_PA15AX
FLEXCOM71DTXDPIO_PC0C–
DRXDPIO_PC1CX
FLEXCOM81DTXDPIO_PB4B–
DRXDPIO_PB5BX
FLEXCOM91DTXDPIO_PC8C–
DRXDPIO_PC9CX
FLEXCOM101DTXDPIO_PC16C–
DRXDPIO_PC17CX
FLEXCOM111DTXDPIO_PB15C–
DRXDPIO_PB16CX
FLEXCOM121DTXDPIO_PB17C–
DRXDPIO_PB18CX