9.4.6.5 Data Strobe Delay Management

When DQS/DS is output by the memory edge-aligned with read data, the QSPI must delay the signal by an appropriate value to correctly sample the data sent by the memory.

The QSPI embeds a delay circuitry that must be enabled by writing QSPI_MR.DQSDLYEN to 1 prior to enabling the QSPI. DQS/DS management must be also be enabled by writing QSPI_IFR.DQSEN=1.

Periodically, the delay line must be calibrated. The calibration can be performed automatically or manually through a refresh. The calibration process is described in the section Refresh Sequence.