| Active Controller |
The Controller device that is currently in control of the I3C
bus |
| Address Header |
A data sequence on the bus that follows a Start or Restart and
includes 7 Address bits, one R/W bit, and one
ACK/NACK bit |
| Arbitration |
A method used to determine which device has bus control if multiple
devices started transmitting at the same time. It can also be required
during Target transmission if a Controller addresses multiple
Targets. |
| Broadcast |
A command or message intended for multiple Target devices and uses
the Broadcast Address 7’h7E |
| Broadcast Address |
A reserved 7-bit address transmitted by the Controller with the value
of 7’h7E as part of a Broadcast message (see
“Broadcast”) |
| Common Command Code (CCC) |
Globally supported standardized commands that the Controller can
transmit either directly to a specific target (Direct CCC) or broadcast
to all targets on the bus simultaneously (Broadcast CCC) |
| Controller |
A device which has control over the I3C bus (timing and data) |
| Data Word |
A data sequence, typically occurring after the Address Header, for
transmitting data on the bus and includes nine consecutive bits
consisting of 8-bits of data and one T-bit |
| Defining Byte |
Additional byte to further describe the configuration of a
CCC |
| Device |
Either a Controller or Target |
| Dynamic Address |
A device address assigned to the Target by the Active Controller
during the initialization of the bus or the Target device; typically
happens after power up |
| Frame |
A data transfer sequence starting with a Start and ending with a
Stop |
| High Data Rate (HDR) |
A data transfer that occurs using both edges of the clock to achieve
higher speeds |
| Hot-Join |
A feature which allows a Target device to join the I3C bus after the
bus has been configured and to notify the Controller device that it is
ready to receive a Dynamic Address |
| I3C® Bus (or Bus) |
The physical and logical implementation of the Serial Data (SDA) and
Serial Clock (SCL) |
| In-Band Interrupt (IBI) |
A method where a Target device generates an interrupt for the
Controller to service using the I3C bus (without using any external
interrupt lines) |
| Legacy I2C Target |
A Target device that meets the requirements of the I2C
Specification |
| Legacy I2C transaction |
A typical I2C transaction that occurs on the I3C
bus |
| Message |
A communication packet between devices on the bus |
| Offline Capable |
A device capable of disconnecting from the I3C bus physically or
capable of ignoring I3C traffic on the bus |
| Open-Drain |
A High Impedance state of an output driver with an active pull-down
and typically used with a passive pull-up; used for signaling of
I2C communication and some I3C communication |
| Pad Buffer |
An I/O buffer available on the SDA and SCL pads that meets the
voltage and speed requirements for the desired communication type (like
I3C, I2C, SMBus) |
| Peripheral |
Another way of referring to this Target Module |
| Primary Controller |
The Controller-capable I3C device that initializes the I3C bus and
performs configuration of all target devices. It acts as the authority
for the bus in its initial state and becomes the first Active Controller
once the bus is configured. |
| Private Transaction |
A transaction that happens exclusively between the Controller and the
Target that is not a CCC, IBI, or Hot-Join transaction |
| Push-Pull |
An output driver with active pull-down and active pull-up; primary
method of signaling for I3C communication |
| Restart |
A signal that looks identical to a Start and can be used as an
alternative to a Stop to be able to send multiple messages in the same
frame |
| Secondary Controller |
A Controller-capable I3C device that initially acts as a Target, but
can accept Controller-ship from the Active Controller and become the new
Active Controller |
| Signaling |
A method of pulling the SDA and SCL lines high or low
to transmit data on the bus, see “Open-Drain” or “Push-Pull” |
| Single Data Rate (SDR) |
Data transfer that occurs using only one edge of the clock |
| Speed-Limited |
A device that is unable to meet one or more timing requirements as
per the I3C Specification |
| Spike Filter |
A filter that removes spikes shorter than 50 ns on the bus |
| Start |
A signal asserted by the Controller that is a high-to-low transition
on the SDA line while the SCL line is at a constant high; used to
signify the beginning of a new frame or message |
| Static Address |
A device address that is fixed and cannot be changed |
| Stop |
A signal asserted by the Controller that is a low-to-high transition
on the SDA line while the SCL line is at a constant high; used to
signify the end of a frame or message |
| Target |
A device that can only respond to a command or message from a
Controller device and cannot generate clock pulses |
