22.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below).

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 22-1. PPS Input Selection Table
Peripheral PPS Input Register 14-Pin Devices 20-Pin Devices
Default Pin Selection at POR Register Reset Value at POR Available Input Port Default Pin Selection at POR Register Reset Value at POR Available Input Port
Interrupt 0 INT0PPS RA2 ‘b000 010 A — C W RA2 ‘b000 010 A B C W
Interrupt 1 INT1PPS RA4 ‘b000 100 A — C W RA4 ‘b000 100 A B C W
Interrupt 2 INT2PPS RA5 ‘b000 101 A — C W RA5 ‘b000 101 A B C W
Timer0 Clock T0CKIPPS RA2 ‘b000 010 A — C W RA2 ‘b000 010 A B C W
Timer1 Clock T1CKIPPS RA5 ‘b000 101 A — C W RA5 ‘b000 101 A B C W
Timer1 Gate T1GPPS RA4 ‘b000 100 A — C W RA4 ‘b000 100 A B C W
Timer2 Input T2INPPS RA5 ‘b000 101 A — C W RA5 ‘b000 101 A B C W
Timer4 Input T4INPPS RC1 ‘b010 001 A — C W RC1 ‘b010 001 A B C W
Universal Timer Input 0 TUIN0PPS RA1 ‘b000 001 A — C W RA1 ‘b000 001 A B C W
Universal Timer Input 1 TUIN1PPS RC0 ‘b010 000 A — C W RC0 ‘b010 000 A B C W
CCP1 CCP1PPS RC5 ‘b010 101 A — C W RC5 ‘b010 101 A B C W
CCP2 CCP2PPS RC3 ‘b010 011 A — C W RC3 ‘b010 011 A B C W
PWM Input 0 PWMIN0PPS RC5 ‘b010 101 A — C W RC5 ‘b010 101 A B C W
PWM Input 1 PWMIN1PPS RC3 ‘b010 011 A — C W RC3 ‘b010 011 A B C W
PWM1 External Reset Source PWM1ERSPPS RA5 ‘b000 101 A — C W RA5 ‘b000 101 A B C W
PWM2 External Reset Source PWM2ERSPPS RC1 ‘b010 001 A — C W RC1 ‘b010 001 A B C W
CWG1 CWG1PPS RA2 ‘b000 010 A — C — RA2 ‘b000 010 A B C —
CLCx Input 1 CLCIN0PPS RC3 ‘b010 011 A — C W RA2 ‘b000 010 A B C W
CLCx Input 2 CLCIN1PPS RC4 ‘b010 100 A — C W RC3 ‘b010 011 A B C W
CLCx Input 3 CLCIN2PPS RC1 ‘b010 001 A — C W RB6 ‘b001 110 A B C W
CLCx Input 4 CLCIN3PPS RA5 ‘b000 101 A — C W RB5 ‘b001 101 A B C W
UART1 Receive U1RXPPS RC5 ‘b010 101 A — C W RB5 ‘b001 101 A B C W
UART1 Clear to Send U1CTSPPS RC4 ‘b010 100 A — C — RB7 ‘b001 111 A B C —
UART2 Receive U2RXPPS RC1 ‘b010 001 A — C W RC1 ‘b010 001 A B C W
UART2 Clear to Send U2CTSPPS RC0 ‘b010 000 A — C — RC0 ‘b010 000 A B C —
SPI1 Clock SPI1SCKPPS RC0 ‘b010 000 A — C W RB6 ‘b001 110 A B C W
SPI1 Data SPI1SDIPPS RC1 ‘b010 001 A — C W RB5 ‘b001 101 A B C W
SPI1 Client Select SPI1SSPPS RC3 ‘b010 011 A — C W RC6 ‘b010 110 A B C W
I2C1 Clock I2C1SCLPPS(1) RC0 ‘b010 000 A — C — RB6 ‘b001 110 A B C —
I2C1 Data I2C1SDAPPS(1) RC1 ‘b010 001 A — C — RB5 ‘b001 101 A B C —
ADC Auto-Conversion Trigger ADACTPPS RC3 ‘b010 011 A — C W RC3 ‘b010 011 A B C W
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.