42.1.1 Standard Instruction Set 

Important: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes:

{label} instruction argument(s).


ADDFSR	Add Literal to FSR
Syntax	`ADDFSR f_n, k`
Operands	0 ≤ k ≤ 63 f_n ∈ [0, 1, 2]
Operation	(FSRf_n) + k → FSRf_n
Status Affected	None
Encoding	`1110`	`1000`	`f_nf_nkk`	`kkkk`
Description	The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f_n’
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to FSR

Example: ADDFSR 2, 23h

Before Instruction
FSR2 = 03FFh

After Instruction
FSR2 = 0422h


ADDLW	Add Literal to W
Syntax	`ADDLW k`
Operands	0 ≤ k ≤ 255
Operation	(W) + k → W
Status Affected	N, OV, C, DC, Z
Encoding	`0000`	`1111`	`kkkk`	`kkkk`
Description	The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to W

Example: ADDLW 15h

Before Instruction
W = 10h

After Instruction
W = 25h


ADDWF	Add W to f
Syntax	`ADDWF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(W) + (f) → dest
Status Affected	N, OV, C, DC, Z
Encoding	`0010`	`01da`	`ffff`	`ffff`
Description	Add W to register ‘f’. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: ADDWF REG, 0, 0

Before Instruction
W = 17h
REG = 0C2h

After Instruction
W = 0D9h
REG = 0C2h


ADDWFC	Add W and Carry Bit to f
Syntax	`ADDWFC f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(W) + (f) + (C) → dest
Status Affected	N, OV, C, DC, Z
Encoding	`0010`	`00da`	`ffff`	`ffff`
Description	Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is placed in data memory location ‘f’. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: ADDWFC REG, 0, 1

Before Instruction
Carry bit = 1
REG = 02h
W = 4Dh

After Instruction
Carry bit = 0
REG = 02h
W = 50h


ANDLW	AND Literal with W
Syntax	`ANDLW k`
Operands	0 ≤ k ≤ 255
Operation	(W) .AND. k → W
Status Affected	N, Z
Encoding	`0000`	`1011`	`kkkk`	`kkkk`
Description	The contents of W are ANDed with the 8-bit literal ‘k’. The result is placed in W
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to W

Example: ANDLW 05Fh

Before Instruction
W = A3h

After Instruction
W = 03h


ANDWF	AND W with f
Syntax	`ANDWF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(W) .AND. (f) → dest
Status Affected	N, Z
Encoding	`0001`	`01da`	`ffff`	`ffff`
Description	The contents of W are ANDed with register ‘f’. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: ANDWF REG, 0, 0

Before Instruction
W = 17h
REG = C2h

After Instruction
W = 02h
REG = C2h


BC	Branch if Carry
Syntax	`BC n`
Operands	-128 ≤ n ≤ 127
Operation	If the Carry bit is ‘`1`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0010`	`nnnn`	`nnnn`
Description	If the Carry bit is ‘`1`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BC 5

Before Instruction
PC = address (HERE)

After Instruction
If Carry = 1; PC = address (HERE + 12)
If Carry = 0; PC = address (HERE + 2)


BCF	Bit Clear f
Syntax	`BCF f, b {,a}`
Operands	0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0, 1]
Operation	0 → f<b>
Status Affected	None
Encoding	`1001`	`bbba`	`ffff`	`ffff`
Description	Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write register ‘f’

Example: BCF FLAG_REG, 7, 0

Before Instruction
FLAG_REG = C7h

After Instruction
FLAG_REG = 47h


BN	Branch if Negative
Syntax	`BN n`
Operands	-128 ≤ n ≤ 127
Operation	If NEGATIVE bit is ‘`1`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0110`	`nnnn`	`nnnn`
Description	If the NEGATIVE bit is ‘`1`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BN Jump

Before Instruction
PC = address (HERE)

After Instruction
If NEGATIVE = 1; PC = address (Jump)
If NEGATIVE = 0; PC = address (HERE + 2)


BNC	Branch if Not Carry
Syntax	`BNC n`
Operands	-128 ≤ n ≤ 127
Operation	If the Carry bit is ‘`0`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0011`	`nnnn`	`nnnn`
Description	If the Carry bit is ‘`0`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BNC Jump

Before Instruction
PC = address (HERE)

After Instruction
If Carry = 0; PC = address (Jump)
If Carry = 1; PC = address (HERE + 2)


BNN	Branch if Not Negative
Syntax	`BNN n`
Operands	-128 ≤ n ≤ 127
Operation	If NEGATIVE bit is ‘`0`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0111`	`nnnn`	`nnnn`
Description	If the NEGATIVE bit is ‘`0`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BNN Jump

Before Instruction
PC = address (HERE)

After Instruction
If NEGATIVE = 0; PC = address (Jump)
If NEGATIVE = 1; PC = address (HERE + 2)


BNOV	Branch if Not Overflow
Syntax	`BNOV n`
Operands	-128 ≤ n ≤ 127
Operation	If OVERFLOW bit is ‘`0`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0101`	`nnnn`	`nnnn`
Description	If the OVERFLOW bit is ‘`0`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BNOV Jump

Before Instruction
PC = address (HERE)

After Instruction
If OVERFLOW = 0; PC = address (Jump)
If OVERFLOW = 1; PC = address (HERE + 2)


BNZ	Branch if Not Zero
Syntax	`BNZ n`
Operands	-128 ≤ n ≤ 127
Operation	If ZERO bit is ‘`0`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0001`	`nnnn`	`nnnn`
Description	If the ZERO bit is ‘`0`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BNZ Jump

Before Instruction
PC = address (HERE)

After Instruction
If ZERO = 0; PC = address (Jump)
If ZERO = 1; PC = address (HERE + 2)


BOV	Branch if Overflow
Syntax	`BOV n`
Operands	-128 ≤ n ≤ 127
Operation	If OVERFLOW bit is ‘`1`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0100`	`nnnn`	`nnnn`
Description	If the OVERFLOW bit is ‘`1`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BOV Jump

Before Instruction
PC = address (HERE)

After Instruction
If OVERFLOW = 1; PC = address (Jump)
If OVERFLOW = 0; PC = address (HERE + 2)


BRA	Unconditional Branch
Syntax	`BRA n`
Operands	-1024 ≤ n ≤ 1023
Operation	(PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1101`	`0nnn`	`nnnn`	`nnnn`
Description	The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

Example: HERE BRA Jump

Before Instruction
PC = address (HERE)

After Instruction
PC = address (Jump)


BSF	Bit Set f
Syntax	`BSF f, b {,a}`
Operands	0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0, 1]
Operation	1 → f<b>
Status Affected	None
Encoding	`1000`	`bbba`	`ffff`	`ffff`
Description	Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write register ‘f’

Example: BSF FLAG_REG, 7, 1

Before Instruction
FLAG_REG = 0Ah

After Instruction
FLAG_REG = 8Ah


BTFSC	Bit Test File, Skip if Clear
Syntax	`BTFSC f, b {,a}`
Operands	0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0, 1]
Operation	Skip if (f<b>) = `0`
Status Affected	None
Encoding	`1011`	`bbba`	`ffff`	`ffff`
Description	If bit ‘b’ in register ‘f’ is ‘`0`’, then the next instruction is skipped. If bit ‘b’ is ‘`0`’, then the next instruction fetched during the current instruction execution is discarded and a `NOP` is executed instead, making this a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   BTFSC   FLAG, 1, 0
FALSE:
TRUE:

Before Instruction
PC = address (HERE)

After Instruction
If FLAG<1> = 0; PC = address (TRUE)
If FLAG<1> = 1; PC = address (FALSE)


BTFSS	Bit Test File, Skip if Set
Syntax	`BTFSS f, b {,a}`
Operands	0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0, 1]
Operation	Skip if (f<b>) = `1`
Status Affected	None
Encoding	`1010`	`bbba`	`ffff`	`ffff`
Description	If bit ‘b’ in register ‘f’ is ‘`1`’, then the next instruction is skipped. If bit ‘b’ is ‘`1`’, then the next instruction fetched during the current instruction execution is discarded and a `NOP` is executed instead, making this a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   BTFSS   FLAG, 1, 0
FALSE:
TRUE:

Before Instruction
PC = address (HERE)

After Instruction
If FLAG<1> = 0; PC = address (FALSE)
If FLAG<1> = 1; PC = address (TRUE)


BTG	Bit Toggle f
Syntax	`BTG f, b {,a}`
Operands	0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0, 1]
Operation	(f<b>) → f<b>
Status Affected	None
Encoding	`0111`	`bbba`	`ffff`	`ffff`
Description	Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write register ‘f’

Example: BTG PORTC, 4, 0

Before Instruction
PORTC = 0111 0101 [75h]

After Instruction
PORTC = 0110 0101 [65h]


BZ	Branch if Zero
Syntax	`BZ n`
Operands	-128 ≤ n ≤ 127
Operation	If ZERO bit is ‘`1`’ (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1110`	`0000`	`nnnn`	`nnnn`
Description	If the ZERO bit is ‘`1`’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words	1
Cycles	1 (2)

Q Cycle Activity:

If Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	Write to PC
No operation	No operation	No operation	No operation

If No Jump:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’	Process Data	No operation

Example: HERE BOV Jump

Before Instruction
PC = address (HERE)

After Instruction
If ZERO = 1; PC = address (Jump)
If ZERO = 0; PC = address (HERE + 2)


CALL	Subroutine Call
Syntax	`CALL k {,s}`
Operands	0 ≤ k ≤ 1048575 s ∈ [0, 1]
Operation	(PC) + 4 → TOS k → PC<20:1> If s = `1` (W) → WREG_CSHAD (STATUS) → STATUS_CSHAD (BSR) → BSR_CSHAD
Status Affected	None
Encoding 1st word (k<7:0>) 2nd word (k<19:8>)	`1110`	`110s`	`k₇kkk`	`kkkk₀`
Encoding 1st word (k<7:0>) 2nd word (k<19:8>)	`1111`	`k₁₉kkk`	`kkkk`	`kkkk₈`
Description	Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If ‘s’ = `1`, the WREG, STATUS and BSR registers are also pushed into their respective shadow registers WREG_CSHAD, STATUS_CSHAD and BSR_CSHAD. If ‘s’ = `0`, no update occurs (default). Then, the 20-bit value ‘k’ is loaded into PC<20:1>. CALL is a two-cycle instruction.
Words	2
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’<7:0>	PUSH PC to stack	Read literal ‘k’<19:8> Write to PC
No operation	No operation	No operation	No operation

Example: HERE CALL THERE, 1

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)
TOS = address (HERE + 4)
WREG_CSHAD = (WREG)
BSR_CSHAD = (BSR)
STATUS_CSHAD = (STATUS)


CALLW	Subroutine Call using WREG
Syntax	`CALLW`
Operands	None
Operation	(PC) + 2 → TOS (W) → PCL (PCLATH) → PCH (PCLATU) → PCU
Status Affected	None
Encoding	`0000`	`0000`	`0001`	`0100`
Description	First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched onto PCH and PCU respectively. The second cycle is executed as a `NOP` instruction while the new next instruction is fetched. Unlike `CALL`, there is no option to update W, STATUS or BSR.
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read WREG	PUSH PC to stack	No operation
No operation	No operation	No operation	No operation

Example: HERE CALLW

Before Instruction

PC = address (HERE)
PCLATH = 10h
PCLATU = 00h
W = 06h

After Instruction

PC = address 001006h
TOS = address (HERE + 2)
PCLATH = 10h
PCLATU = 00h
W = 06h


CLRF	Clear f
Syntax	`CLRF f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	`000h` → f `1` → Z
Status Affected	Z
Encoding	`0110`	`101a`	`ffff`	`ffff`
Description	Clears the contents of the specified register ‘f’. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write register ‘f’

Example: CLRF FLAG_REG, 1

Before Instruction
FLAG_REG = 5Ah

After Instruction
FLAG_REG = 00h


CLRWDT	Clear Watchdog Timer
Syntax	`CLRWDT`
Operands	None
Operation	`000h` → WDT `1` → TO `1` → PD
Status Affected	TO, PD
Encoding	`0000`	`0000`	`0000`	`0100`
Description	`CLRWDT` instruction resets the Watchdog Timer. It also resets the STATUS bits, and TO and PD are set.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	Process Data	No operation

Example: CLRWDT

Before Instruction
WDT Counter = ?

After Instruction
WDT Counter = 00h
TO = 1
PD = 1


COMF	Complement f
Syntax	`COMF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) → dest
Status Affected	N, Z
Encoding	`0001`	`11da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are complemented. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: COMF REG0, 0, 0

Before Instruction
REG = 13h

After Instruction
REG = 13h
W = ECh


CPFSEQ	Compare f with W, Skip if f = W
Syntax	`CPFSEQ f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	(f) – (W), skip if (f) = (W) (unsigned comparison)
Status Affected	None
Encoding	`0110`	`001a`	`ffff`	`ffff`
Description	Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are equal to the contents of WREG, then the fetched instruction is discarded and a `NOP` is executed instead, making this a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   CPFSEQ   REG, 0
NEQUAL:
EQUAL:

Before Instruction
PC = address (HERE)
W = ?
REG = ?

After Instruction
If REG = W; PC = address (EQUAL)
If REG ≠ W; PC = address (NEQUAL)


CPFSGT	Compare f with W, Skip if f > W
Syntax	`CPFSGT f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	(f) – (W), skip if (f) > (W) (unsigned comparison)
Status Affected	None
Encoding	`0110`	`010a`	`ffff`	`ffff`
Description	Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched instruction is discarded and a `NOP` is executed instead, making this a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   CPFSGT   REG, 0
NGREATER:
GREATER:

Before Instruction
PC = address (HERE)
W = ?
REG = ?

After Instruction
If REG > W; PC = address (GREATER)
If REG ≤ W; PC = address (NGREATER)


CPFSLT	Compare f with W, Skip if f < W
Syntax	`CPFSLT f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	(f) – (W), skip if (f) < (W) (unsigned comparison)
Status Affected	None
Encoding	`0110`	`000a`	`ffff`	`ffff`
Description	Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are less than the contents of WREG, then the fetched instruction is discarded and a `NOP` is executed instead, making this a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   CPFSLT   REG, 1
NLESS:
LESS:

Before Instruction
PC = address (HERE)
W = ?
REG = ?

After Instruction
If REG < W; PC = address (LESS)
If REG ≥ W; PC = address (NLESS)


DAW	Decimal Adjust W Register
Syntax	`DAW`
Operands	None
Operation	If [(W<3:0>) > 9] or [DC = `1`] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0>; If [(W<7:4>) + DC > 9] or [C = `1`] then (W<7:4>) + 6 + DC → W<7:4>; else (W<7:4>) + DC → W<7:4>
Status Affected	C
Encoding	`0000`	`0000`	`0000`	`0111`
Description	`DAW` adjusts the 8-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register W	Process Data	Write register W

Example 1: DAW

Before Instruction
W = A5h
C = 0
DC = 0

After Instruction
W = 05h
C = 1
DC = 0

Example 2: DAW

Before Instruction
W = CEh
C = 0
DC = 0

After Instruction
W = 34h
C = 1
DC = 0


DECF	Decrement f
Syntax	`DECF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) – 1 → dest
Status Affected	C, DC, N, OV, Z
Encoding	`0000`	`01da`	`ffff`	`ffff`
Description	Decrement register ‘f’. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: DECF CNT, 1, 0

Before Instruction
CNT = 01h
Z = 0

After Instruction
CNT = 00h
Z = 1


DECFSZ	Decrement f, Skip if 0
Syntax	`DECFSZ f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) – 1 → dest, skip if result = `0`
Status Affected	None
Encoding	`0010`	`11da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are decremented. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’ (default). If the result is ‘`0`’, the next instruction, which is already fetched, is discarded and a `NOP` is executed instead, making it a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   DECFSZ   CNT, 1, 1
       GOTO     LOOP
CONTINUE

Before Instruction
CNT = ?
PC = address (HERE)

After Instruction
CNT = CNT – 1
If CNT = 0; PC = address (CONTINUE)
If CNT ≠ 0; PC = address (HERE + 2)


DCFSNZ	Decrement f, Skip if not 0
Syntax	`DCFSNZ f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) – 1 → dest, skip if result ≠ `0`
Status Affected	None
Encoding	`0100`	`11da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are decremented. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’ (default). If the result is not ‘`0`’, the next instruction, which is already fetched, is discarded and a `NOP` is executed instead, making it a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   DCFSNZ   TEMP, 1, 0
ZERO:
NZERO:

Before Instruction
TEMP = ?
PC = address (HERE)

After Instruction
TEMP = TEMP – 1
If TEMP = 0; PC = address (ZER0)
If TEMP ≠ 0; PC = address (NZERO)


GOTO	Unconditional Branch
Syntax	`GOTO k`
Operands	0 ≤ k ≤ 1048575
Operation	k → PC<20:1>
Status Affected	None
Encoding 1st word (k<7:0>) 2nd word (k<19:8>)	`1110`	`1111`	`k₇kkk`	`kkkk₀`
Encoding 1st word (k<7:0>) 2nd word (k<19:8>)	`1111`	`k₁₉kkk`	`kkkk`	`kkkk₈`
Description	`GOTO` allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC<20:1>. `GOTO` is always a two-cycle instruction.
Words	2
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’<7:0>	No operation	Read literal ‘k’<19:8> Write to PC
No operation	No operation	No operation	No operation

Example: HERE GOTO THERE

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)


INCF	Increment f
Syntax	`INCF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) + 1 → dest
Status Affected	C, DC, N, OV, Z
Encoding	`0010`	`10da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are incremented. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: INCF CNT, 1, 0

Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?

After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1


INCFSZ	Increment f, Skip if 0
Syntax	`INCFSZ f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) + 1 → dest, skip if result = `0`
Status Affected	None
Encoding	`0011`	`11da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are incremented. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’ (default). If the result is ‘`0`’, the next instruction, which is already fetched, is discarded and a `NOP` is executed instead, making it a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   INCFSZ   CNT, 1, 0
NZERO:
ZERO:

Before Instruction
CNT = ?
PC = address (HERE)

After Instruction
CNT = CNT + 1
If CNT = 0; PC = address (ZERO)
If CNT ≠ 0; PC = address (NZERO)


INFSNZ	Increment f, Skip if not 0
Syntax	`INFSNZ f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) + 1 → dest, skip if result ≠ `0`
Status Affected	None
Encoding	`0100`	`10da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are incremented. If ‘d’ is ‘`0`’, the result is placed in W. If ‘d’ is ‘`1`’, the result is placed back in register ‘f’ (default). If the result is not ‘`0`’, the next instruction, which is already fetched, is discarded and a `NOP` is executed instead, making it a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   INFSNZ   REG, 1, 0
ZERO:
NZERO:

Before Instruction
REG = ?
PC = address (HERE)

After Instruction
REG = REG + 1
If REG = 0; PC = address (ZER0)
If REG ≠ 0; PC = address (NZERO)


IORLW	Inclusive OR Literal with W
Syntax	`IORLW k`
Operands	0 ≤ k ≤ 255
Operation	(W) .OR. k → W
Status Affected	N, Z
Encoding	`0000`	`1001`	`kkkk`	`kkkk`
Description	The contents of W are ORed with the 8-bit literal ‘k’. The result is placed in W.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to W

Example: IORLW 35h

Before Instruction
W = 9Ah

After Instruction
W = BFh


IORWF	Inclusive OR W with f
Syntax	`IORWF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(W) .OR. (f) → dest
Status Affected	N, Z
Encoding	`0001`	`00da`	`ffff`	`ffff`
Description	Inclusive OR W with register ‘f’. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: IORWF RESULT, 0, 1

Before Instruction
RESULT = 13h
W = 91h

After Instruction
RESULT = 13h
W = 93h


LFSR	Load FSR
Syntax	`LFSR f_n, k`
Operands	0 ≤ f_n ≤ 2 0 ≤ k ≤ 16383
Operation	k → FSRf_n
Status Affected	None
Encoding	`1110`	`1110`	`00f_nf_n`	`k₁₃kkk₁₀`
Encoding	`1111`	`00k₉k`	`kkkk`	`kkkk₀`
Description	The 14-bit literal ‘k’ is loaded into the File Select Register ‘f_n’
Words	2
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’<13:10>	Process Data	Write literal ‘k’<13:10> to FSRf_n<13:10>
No operation	Read literal ‘k’<9:0>	No operation	Write literal ‘k’<9:0> to FSRf_n<9:0>

Example: LFSR 2, 3ABh

Before Instruction
FSR2H = ?
FSR2L = ?

After Instruction
FSR2H = 03h
FSR2L = ABh


MOVF	Move f
Syntax	`MOVF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) → dest
Status Affected	N, Z
Encoding	`0101`	`00da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are moved to a destination. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: MOVF REG, 0, 0

Before Instruction
REG = 22h
W = FFh

After Instruction
REG = 22h
W = 22h


MOVFF	Move f to f
Syntax	`MOVFF f_s, f_d`
Operands	0 ≤ f_s ≤ 4095 0 ≤ f_d ≤ 4095
Operation	(f_s) → f_d
Status Affected	None
Encoding	`1100`	`f_sf_sf_sf_s`	`f_sf_sf_sf_s`	`f_sf_sf_sf_s`
Encoding	`1111`	`f_df_df_df_d`	`f_df_df_df_d`	`f_df_df_df_d`
Description	The contents of source register ‘f_s’ are moved to destination register ‘f_d’. Location of source ‘f_s’ can be anywhere in the 4096-byte data space (`000h` to `FFFh`) and location of destination ‘f_d’ can also be anywhere from `000h` to `FFFh`. `MOVFF` is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The `MOVFF` instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Note: `MOVFF` has curtailed the source and destination range to the lower 4 Kbyte space of memory (Banks 1 through 15). For everything else, use `MOVFFL`.
Words	2
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f_s’	Process Data	No operation
Decode	No operation No dummy read	No operation	Write register ‘f_d’

Example: MOVFF REG1, REG2

Before Instruction
Address of REG1 = 100h
Address of REG2 = 200h
REG1 = 33h
REG2 = 11h

After Instruction
Address of REG1 = 100h
Address of REG2 = 200h
REG1 = 33h
REG2 = 33h


MOVFFL	Move f to f (Long Range)
Syntax	`MOVFFL f_s, f_d`
Operands	0 ≤ f_s ≤ 16383 0 ≤ f_d ≤ 16383
Operation	(f_s) → f_d
Status Affected	None
Encoding	`0000`	`0000`	`0110`	`f_sf_sf_sf_s`
	`1111`	`f_sf_sf_sf_s`	`f_sf_sf_sf_s`	`f_sf_sf_df_d`
	`1111`	`f_df_df_df_d`	`f_df_df_df_d`	`f_df_df_df_d`
Description	The contents of source register ‘f_s’ are moved to destination register ‘f_d’. Location of source ‘f_s’ can be anywhere in the 16 Kbyte data space (`0000h` to `3FFFh`) and location of destination ‘f_d’ can also be anywhere from `0000h` to `3FFFh`. Either source or destination can be W (a useful special situation). `MOVFFL` is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The `MOVFFL` instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register.
Words	3
Cycles	3

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	No operation	No operation
Decode	Read register ‘f_s’	Process Data	No operation
Decode	No operation No dummy read	No operation	Write register ‘f_d’

Example: MOVFFL 2000h, 200Ah

Before Instruction
Contents of 2000h = 33h
Contents of 200Ah = 11h

After Instruction
Contents of 2000h = 33h
Contents of 200Ah = 33h


MOVLB	Move Literal to BSR
Syntax	`MOVLB k`
Operands	0 ≤ k ≤ 63
Operation	k → BSR
Status Affected	None
Encoding	`0000`	`0001`	`00kk`	`kkkk`
Description	The 6-bit literal ‘k’ is loaded into the Bank Select Register (BSR<5:0>). The value of BSR<7:6> always remains ‘`0`’.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to BSR

Example: MOVLB 5

Before Instruction
BSR = 02h

After Instruction
BSR = 05h


MOVLW	Move Literal to W
Syntax	`MOVLW k`
Operands	0 ≤ k ≤ 255
Operation	k → W
Status Affected	None
Encoding	`0000`	`1110`	`kkkk`	`kkkk`
Description	The 8-bit literal ‘k’ is loaded into W
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to W

Example: MOVLW 5Ah

Before Instruction
W = ?

After Instruction
W = 5Ah


MOVWF	Move W to f
Syntax	`MOVWF f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	(W) → f
Status Affected	None
Encoding	`0110`	`111a`	`ffff`	`ffff`
Description	Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read W	Process Data	Write register ‘f’

Example: MOVWF REG, 0

Before Instruction
W = 4Fh
REG = FFh

After Instruction
W = 4Fh
REG = 4Fh


MULLW	Multiply literal with W
Syntax	`MULLW k`
Operands	0 ≤ k ≤ 255
Operation	(W) x k → PRODH:PRODL
Status Affected	None
Encoding	`0000`	`1101`	`kkkk`	`kkkk`
Description	An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write registers PRODH:PRODL

Example: MULLW 0C4h

Before Instruction
W = E2h
PRODH = ?
PRODL = ?

After Instruction
W = E2h
PRODH = ADh
PRODL = 08h


MULWF	Multiply W with f
Syntax	`MULWF f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	(W) x (f) → PRODH:PRODL
Status Affected	None
Encoding	`0000`	`001a`	`ffff`	`ffff`
Description	An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and ‘f’ are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write registers PRODH:PRODL

Example: MULWF REG, 1

Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?

After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h


NEGF	Negate f
Syntax	`NEGF f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	(f) + 1 → f
Status Affected	N, OV, C, DC, Z
Encoding	`0110`	`110a`	`ffff`	`ffff`
Description	Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write register ‘f’

Example: NEGF REG, 1

Before Instruction
REG = 0011 1010 [3Ah]

After Instruction
REG = 1100 0110 [C6h]


NOP	No Operation
Syntax	`NOP`
Operands	None
Operation	No operation
Status Affected	None
Encoding	`0000`	`0000`	`0000`	`0000`
Encoding	`1111`	`xxxx`	`xxxx`	`xxxx`
Description	No operation
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	No operation	No operation

Example: None.


POP	Pop Top of Return Stack
Syntax	`POP`
Operands	None
Operation	(TOS) → bit bucket
Status Affected	None
Encoding	`0000`	`0000`	`0000`	`0110`
Description	The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack (see the `PUSH` instruction description).
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	POP TOS value	No operation

Example:

    POP
    GOTO    NEW

Before Instruction
TOS = 0031A2h
Stack (1 level down) = 014332h

After Instruction
TOS = 014332h
PC = address (NEW)


PUSH	Push Top of Return Stack
Syntax	`PUSH`
Operands	None
Operation	(PC) + 2 → TOS
Status Affected	None
Encoding	`0000`	`0000`	`0000`	`0101`
Description	The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack (see the `POP` instruction description).
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	PUSH PC + 2 onto return stack	No operation	No operation

Example: PUSH

Before Instruction
TOS = 00345Ah
PC = 000124h

After Instruction
TOS = 000126h
PC = 000126h
Stack (1 level down) = 00345Ah


RCALL	Relative Call
Syntax	`RCALL n`
Operands	-1024 ≤ n ≤ 1023
Operation	(PC) + 2 → TOS (PC) + 2 + 2n → PC
Status Affected	None
Encoding	`1101`	`1nnn`	`nnnn`	`nnnn`
Description	Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the two’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘n’ PUSH PC to stack	Process Data	Write to PC
No operation	No operation	No operation	No operation

Example: HERE RCALL Jump

Before Instruction
PC = address (HERE)

After Instruction
PC = address (Jump)
TOS = address (HERE + 2)


RESET	Reset
Syntax	`RESET`
Operands	None
Operation	Reset all registers and flags that are affected by a MCLR Reset
Status Affected	All
Encoding	`0000`	`0000`	`1111`	`1111`
Description	This instruction provides a way to execute a MCLR Reset by software
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Start Reset	No operation	No operation

Example: RESET

Before Instruction
All Registers = ?
All Flags = ?

After Instruction
All Registers = Reset Value
All Flags = Reset Value


RETFIE	Return from Interrupt
Syntax	`RETFIE {s}`
Operands	s ∈ [0, 1]
Operation	(TOS) → PC If s = `1`, context is restored into WREG, STATUS, BSR, FSR0H, FSR0L, FSR1H, FSR1L, FSR2H, FSR2L, PRODH, PRODL, PCLATH and PCLATU registers from the corresponding shadow registers. If s = `0`, there is no change in status of any register. PCLATU, PCLATH are unchanged.
Status Affected	STAT bits in INTCONx register
Encoding	`0000`	`0000`	`0001`	`000s`
Description	Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high- or low-priority Global Interrupt Enable bit. If ‘s’ = `1`, the contents of the shadow registers WREG_SHAD, STATUS_SHAD, BSR_SHAD, FSR0H_SHAD, FSR0L_SHAD, FSR1H_SHAD, FSR1L_SHAD, FSR2H_SHAD, FSR2L_SHAD, PRODH_SHAD, PRODL_SHAD, PCLATH_SHAD and PCLATU_SHAD are loaded into corresponding registers. There are two sets of shadow registers, main context and low context. The set retrieved on `RETFIE` instruction execution depends on what the state of operation of the CPU was when `RETFIE` was executed. If ‘s’ = `0`, no update of these registers occurs (default). The upper and high address latches (PCLATU/H) remain unchanged.
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	Process Data	POP PC from stack
No operation	No operation	No operation	No operation

Example: RETFIE 1

After Instruction
PC = (TOS)
WREG = (WREG_SHAD)
BSR = (BSR_SHAD)
STATUS = (STATUS_SHAD)
FSR0H/L = (FSR0H/L_SHAD)
FSR1H/L = (FSR1H/L_SHAD)
FSR2H/L = (FSR2H/L_SHAD)
PRODH/L = (PRODH/L_SHAD)
PCLATH/U = (PCLATH/U_SHAD)


RETLW	Return Literal to W
Syntax	`RETLW k`
Operands	0 ≤ k ≤ 255
Operation	k → W (TOS) → PC PCLATU, PCLATH are unchanged
Status Affected	None
Encoding	`0000`	`1100`	`kkkk`	`kkkk`
Description	W is loaded with the 8-bit literal ‘k’. The Program Counter is loaded from the top of the stack (the return address). The upper and high address latches (PCLATU/H) remain unchanged.
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	POP PC from stack Write to W
No operation	No operation	No operation	No operation

Example:

    CALL   TABLE  ; W contains table offset value
BACK              ; W now has table value (after RETLW)
    :
    :
TABLE
    ADDWF  PCL    ; W = offset
    RETLW  k0     ; Begin table
    RETLW  k1     ;
    :
    :
    RETLW  kn     ; End of table

Before Instruction
W = 07h

After Instruction
W = value of kn


RETURN	Return from Subroutine
Syntax	`RETURN {s}`
Operands	s ∈ [0, 1]
Operation	(TOS) → PC If s = `1` (WREG_CSHAD) → WREG (STATUS_CSHAD) → STATUS (BSR_CSHAD) → BSR PCLATU, PCLATH are unchanged
Status Affected	None
Encoding	`0000`	`0000`	`0001`	`001s`
Description	Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the Program Counter. If ‘s’ = `1`, the contents of the shadow registers WREG_CSHAD, STATUS_CSHAD and BSR_CSHAD, are loaded into their corresponding registers. If ‘s’ = `0`, no update of these registers occurs (default). The upper and high address latches (PCLATU/H) remain unchanged.
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	Process Data	POP PC from stack
No operation	No operation	No operation	No operation

Example: RETURN 1

After Instruction
PC = (TOS)
WREG = (WREG_CSHAD)
BSR = (BSR_CSHAD)
STATUS = (STATUS_CSHAD)


RLCF	Rotate Left f through Carry
Syntax	`RLCF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f<n>) → dest<n+1> (f<7>) → C (C) → dest<0>
Status Affected	C, N, Z
Encoding	`0011`	`01da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: RLCF REG, 0, 0

Before Instruction
REG = 1110 0110 [E6h]
W = ?
C = 0

After Instruction
REG = 1110 0110 [E6h]
W = 1100 1100 [CCh]
C = 1


RLNCF	Rotate Left f (No Carry)
Syntax	`RLNCF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f<n>) → dest<n+1> (f<7>) → dest<0>
Status Affected	N, Z
Encoding	`0100`	`01da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: RLNCF REG, 1, 0

Before Instruction
REG = 1010 1011 [ABh]

After Instruction
REG = 0101 0111 [57h]


RRCF	Rotate Right f through Carry
Syntax	`RRCF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f<n>) → dest<n-1> (f<0>) → C (C) → dest<7>
Status Affected	C, N, Z
Encoding	`0011`	`00da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: RRCF REG, 0, 0

Before Instruction
REG = 1110 0110 [E6h]
W = ?
C = 0

After Instruction
REG = 1110 0110 [E6h]
W = 0111 0011 [73h]
C = 0


RRNCF	Rotate Right f (No Carry)
Syntax	`RRNCF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f<n>) → dest<n-1> (f<0>) → dest<7>
Status Affected	N, Z
Encoding	`0100`	`00da`	`ffff`	`ffff`
Description	The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example 1: RRNCF REG, 1, 0

Before Instruction
REG = 1101 0111 [D7h]

After Instruction
REG = 1110 1011 [EBh]

Example 2: RRNCF REG, 0, 0

Before Instruction
REG = 1101 0111 [D7h]
W = ?

After Instruction
REG = 1101 0111 [D7h]
W = 1110 1011 [EBh]


SETF	Set f
Syntax	`SETF f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	`FFh` → f
Status Affected	None
Encoding	`0110`	`100a`	`ffff`	`ffff`
Description	The contents of the specified register ‘f’ are set to `FFh`. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write register ‘f’

Example: SETF REG, 1

Before Instruction
REG = 5Ah

After Instruction
REG = FFh


SLEEP	Enter Sleep Mode
Syntax	`SLEEP`
Operands	None
Operation	`00h` → WDT 1 → TO 0 → PD
Status Affected	TO, PD
Encoding	`0000`	`0000`	`0000`	`0011`
Description	The Power-down Status (PD) bit is cleared. The Time-Out Status TO) bit is set. Watchdog Timer is cleared. The processor is put into Sleep mode with the oscillator stopped.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	Process Data	Go to Sleep

Example: SLEEP

Before Instruction
TO = ?
PD = ?

After Instruction
TO = 1 †
PD = 0

† If WDT causes wake-up, this bit is cleared.


SUBFSR	Subtract Literal from FSR
Syntax	`SUBFSR f_n, k`
Operands	0 ≤ k ≤ 63 f_n ∈ [0, 1, 2]
Operation	(FSRf_n) – k → FSRf_n
Status Affected	None
Encoding	`1110`	`1001`	`f_nf_nkk`	`kkkk`
Description	The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f_n’
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to FSR

Example: SUBFSR 2, 23h

Before Instruction
FSR2 = 03FFh

After Instruction
FSR2 = 03DCh


SUBFWB	Subtract f from W with Borrow
Syntax	`SUBFWB f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(W) – (f) – (C) → dest
Status Affected	N, OV, C, DC, Z
Encoding	`0101`	`01da`	`ffff`	`ffff`
Description	Subtract register ‘f’ and Carry flag (Borrow) from W (two’s complement method). If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example 1: SUBFWB REG, 1, 0

Before Instruction
REG = 03h
W = 02h
C = 1

After Instruction
REG = FFh (two’s complement)
W = 02h
C = 0
Z = 0
N = 1 (result is negative)

Example 2: SUBFWB REG, 0, 0

Before Instruction
REG = 02h
W = 05h
C = 1

After Instruction
REG = 02h
W = 03h
C = 1
Z = 0
N = 0 (result is positive)

Example 3: SUBFWB REG, 1, 0

Before Instruction
REG = 01h
W = 02h
C = 0

After Instruction
REG = 00h
W = 02h
C = 1
Z = 1 (result is zero)
N = 0


SUBLW	Subtract W from Literal
Syntax	`SUBLW k`
Operands	0 ≤ k ≤ 255
Operation	k – (W) → W
Status Affected	N, OV, C, DC, Z
Encoding	`0000`	`1000`	`kkkk`	`kkkk`
Description	W is subtracted from the 8-bit literal ‘k’. The result is placed in W.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to W

Example 1: SUBLW 02h

Before Instruction
W = 01h
C = ?

After Instruction
W = 01h
C = 1 (result is positive)
Z = 0
N = 0

Example 2: SUBLW 02h

Before Instruction
W = 02h
C = ?

After Instruction
W = 00h
C = 1
Z = 1 (result is zero)
N = 0

Example 3: SUBLW 02h

Before Instruction
W = 03h
C = ?

After Instruction
W = FFh (two’s complement)
C = 0
Z = 0
N = 1 (result is negative)


SUBWF	Subtract W from f
Syntax	`SUBWF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) – (W) → dest
Status Affected	N, OV, C, DC, Z
Encoding	`0101`	`11da`	`ffff`	`ffff`
Description	Subtract W from register ‘f’ (two’s complement method). If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example 1: SUBWF REG, 1, 0

Before Instruction
REG = 03h
W = 02h
C = ?

After Instruction
REG = 01h (two’s complement)
W = 02h
C = 1 (result is positive)
Z = 0
N = 0

Example 2: SUBWF REG, 0, 0

Before Instruction
REG = 02h
W = 02h
C = ?

After Instruction
REG = 02h
W = 00h
C = 1
Z = 1 (result is zero)
N = 0

Example 3: SUBWF REG, 1, 0

Before Instruction
REG = 01h
W = 02h
C = ?

After Instruction
REG = FFh (two’s complement)
W = 02h
C = 0
Z = 0
N = 1 (result is negative)


SUBWFB	Subtract W from f with Borrow
Syntax	`SUBWFB f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f) – (W) – (C) → dest
Status Affected	N, OV, C, DC, Z
Encoding	`0101`	`10da`	`ffff`	`ffff`
Description	Subtract W and the Carry flag (Borrow) from register ‘f’ (two’s complement method). If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example 1: SUBWFB REG, 1, 0

Before Instruction
REG = 19h (0001 1001)
W = 0Dh (0000 1101)
C = 1

After Instruction
REG = 0Ch (0000 1100)
W = 0Dh (0000 1101)
C = 1 (result is positive)
Z = 0
N = 0

Example 2: SUBWFB REG, 0, 0

Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0

After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 (result is zero)
N = 0

Example 3: SUBWFB REG, 1, 0

Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1110)
C = 1

After Instruction
REG = F5h (1111 0101) (two’s complement)
W = 0Eh (0000 1110)
C = 0
Z = 0
N = 1 (result is negative)


SWAPF	Swap f
Syntax	`SWAPF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(f<3:0>) → dest<7:4> (f<7:4>) → dest<3:0>
Status Affected	None
Encoding	`0011`	`10da`	`ffff`	`ffff`
Description	The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: SWAPF REG, 1, 0

Before Instruction
REG = 53h

After Instruction
REG = 35h


TBLRD	Table Read
Syntax	`TBLRD ` `TBLRD +` `TBLRD -` `TBLRD +`
Operands	None
Operation	If `TBLRD ` (Prog Mem (TBLPTR)) → TABLAT TBLPTR – No Change If `TBLRD +` (Prog Mem (TBLPTR)) → TABLAT (TBLPTR) + 1 → TBLPTR If `TBLRD -` (Prog Mem (TBLPTR)) → TABLAT (TBLPTR) – 1 → TBLPTR If `TBLRD +` (TBLPTR) + 1 → TBLPTR (Prog Mem (TBLPTR)) → TABLAT
Status Affected	None
Encoding	`0000`	`0000`	`0000`	`10mm` `mm=0 ` `mm=1 +` `mm=2 -` `mm=3 +`
Description	This instruction is used to read the contents of Program Memory. To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = `0`: Least Significant Byte of Program Memory Word TBLPTR[0] = `1`: Most Significant Byte of Program Memory Word The `TBLRD` instruction can modify the value of TBLPTR as follows: no change (`TBLRD `) post-increment (`TBLRD +`) post-decrement (`TBLRD -`) pre-increment (`TBLRD +`)
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	No operation	No operation
No operation	No operation (Read Program Memory)	No operation	No operation (Write TABLAT)

Example 1: TBLRD *+

Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
MEMORY (00A356h) = 34h

After Instruction
TABLAT = 34h
TBLPTR = 00A357h

Example 2: TBLRD +*

Before Instruction
TABLAT = AAh
TBLPTR = 01A357h
MEMORY (01A357h) = 12h
MEMORY (01A358h) = 34h

After Instruction
TABLAT = 34h
TBLPTR = 01A358h


TBLWT	Table Write
Syntax	`TBLWT ` `TBLWT +` `TBLWT -` `TBLWT +`
Operands	None
Operation	If `TBLWT ` (TABLAT) → Holding Register TBLPTR – No Change If `TBLWT +` (TABLAT) → Holding Register (TBLPTR) + 1 → TBLPTR If `TBLWT -` (TABLAT) → Holding Register (TBLPTR) – 1 → TBLPTR If `TBLWT +` (TBLPTR) + 1 → TBLPTR (TABLAT) → Holding Register
Status Affected	None
Encoding	`0000`	`0000`	`0000`	`11mm` `mm=0 ` `mm=1 +` `mm=2 -` `mm=3 +`
Description	This instruction uses the three LSBs of TBLPTR to determine which of the eight holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (refer to the “Program Flash Memory” section for additional details on programming Flash memory). The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = `0`: Least Significant Byte of Program Memory Word TBLPTR[0] = `1`: Most Significant Byte of Program Memory Word The `TBLWT` instruction can modify the value of TBLPTR as follows: no change (`TBLWT `) post-increment (`TBLWT +`) post-decrement (`TBLWT -`) pre-increment (`TBLWT +`)
Words	1
Cycles	2

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	No operation	No operation	No operation
No operation	No operation (Read TABLAT)	No operation	No operation (Write to Holding Register)

Example 1: TBLWT *+

Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
HOLDING REGISTER (00A356h) = FFh

After Instruction (table write completion)
TABLAT = 55h
TBLPTR = 00A357h
HOLDING REGISTER (00A356h) = 55h

Example 2: TBLWT +*

Before Instruction
TABLAT = 34h
TBLPTR = 01389Ah
HOLDING REGISTER (01389Ah) = FFh
HOLDING REGISTER (01389Bh) = FFh

After Instruction (table write completion)
TABLAT = 34h
TBLPTR = 01389Bh
HOLDING REGISTER (01389Ah) = FFh
HOLDING REGISTER (01389Bh) = 34h


TSTFSZ	Test f, Skip if 0
Syntax	`TSTFSZ f {,a}`
Operands	0 ≤ f ≤ 255 a ∈ [0, 1]
Operation	Skip if f = `0`
Status Affected	None
Encoding	`0110`	`011a`	`ffff`	`ffff`
Description	If ‘f’ = `0`, the next instruction fetched during the current instruction execution is discarded and a `NOP` is executed, making this a two-cycle instruction. If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction.

Q Cycle Activity:

If no skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation

If skip:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation

If skip and followed by two-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

If skip and followed by three-word instruction:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation
No operation	No operation	No operation	No operation

Example:

HERE   TSTFSZ   CNT, 1
NZERO:
ZERO:

Before Instruction
PC = address (HERE)

After Instruction
If CNT = 0; PC = address (ZERO)
If CNT ≠ 0; PC = address (NZERO)


XORLW	Exclusive OR Literal with W
Syntax	`XORLW k`
Operands	0 ≤ k ≤ 255
Operation	(W) .XOR. k → W
Status Affected	N, Z
Encoding	`0000`	`1010`	`kkkk`	`kkkk`
Description	The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read literal ‘k’	Process Data	Write to W

Example: XORLW 0AFh

Before Instruction
W = B5h

After Instruction
W = 1Ah


XORWF	Exclusive OR W with f
Syntax	`XORWF f {,d {,a}}`
Operands	0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1]
Operation	(W) .XOR. (f) → dest
Status Affected	N, Z
Encoding	`0001`	`10da`	`ffff`	`ffff`
Description	Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘`0`’, the result is stored in W. If ‘d’ is ‘`1`’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘`0`’, the Access Bank is selected. If ‘a’ is ‘`1`’, the BSR is used to select the GPR bank. If ‘a’ is ‘`0`’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ `95` (`5Fh`). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details.
Words	1
Cycles	1

Q Cycle Activity:


Q1	Q2	Q3	Q4
Decode	Read register ‘f’	Process Data	Write to destination

Example: XORWF REG, 1, 0

Before Instruction
REG = AFh
W = B5h

After Instruction
REG = 1Ah
W = B5h