14.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS, PCON0 and PCON1 registers are updated to indicate the cause of the Reset. The following table shows the Reset conditions of these registers.

Table 14-3. Reset Condition for Special Registers
Condition Program
Counter STATUS Register(1,2) PCON0 Register PCON1 Register
VDD Power-on Reset 0 -110 0000 0011 110x ---u u111
VDD Brown-out Reset 0 -110 0000 0011 11u0 ---u uu1u
VDDIO2 Power-on Reset PC + 2 -uuu uuuu uuuu uuuu ---u 0uuu
VDDIO3 Power-on Reset PC + 2 -uuu uuuu uuuu uuuu ---0 uuuu
MCLR Reset during normal operation 0 -uuu uuuu uuuu 0uuu ---u uuuu
MCLR Reset during Sleep 0 -10u uuuu uuuu 0uuu ---u uuuu
WDT Time-out Reset 0 -0uu uuuu uuu0 uuuu ---u uuuu
WDT Wake-up from Sleep PC + 2 -00u uuuu uuuu uuuu ---u uuuu
WWDT Window Violation Reset 0 -uuu uuuu uu0u uuuu ---u uuuu
Interrupt Wake-up from Sleep PC + 2(3) -10u uuuu uuuu uuuu ---u uuuu
RESET Instruction Executed 0 -uuu uuuu uuuu u0uu ---u uuuu
Stack Overflow Reset (STVREN = 1) 0 -uuu uuuu 1uuu uuuu ---u uuuu
Stack Underflow Reset (STVREN = 1) 0 -uuu uuuu u1uu uuuu ---u uuuu
Data Protection (Fuse Fault) 0 -uuu uuuu uuuu uuuu ---u uuu0
VREG or ULP Ready Fault 0 -110 0000 0011 110u ---u u0u1
Memory Violation Reset 0 -uuu uuuu uuuu uuuu ---u uu0u
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note:
  1. If a Status bit is not implemented, that bit will be read as ‘0’.
  2. Status bits Z, C, DC are reset by VDD POR/BOR.
  3. When the wake-up is due to an interrupt and Global Interrupt Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2.